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2017-11-23sb/intel/i82801ix: fetch initial timestamp in bootblockArthur Heymans
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23google/fizz: Define smbios_mainboard_sku to return OEM IDsShelley Chen
Currently, mosys just returns "fizz" as model/chassis values. Returning proper OEM IDs so that mosys can return the proper variant. BUG=b:67732053 BRANCH=None TEST=mosys platform model; mosys platform chassis; Make sure returns the right variant string and not fizz. Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22google/gru: Add support for rainierEge Mihmanli
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using GRU_BASEBOARD_SCARLET is enough, except for display related logic. In those cases, use board specific logic instead of baseboard. Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/22542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20mainboard/google/fizz: Enable separate MRC cache for recovery modeShelley Chen
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20google/gru: Add config for scarlet-derived boardsEge Mihmanli
There is merit in having new boards use the pinouts and controls in scarlet. This adds a config so new scarlet-derived boards can easily use scarlet structure without going through every file and adding new logic. TEST=Run "emerge-scarlet coreboot" Signed-off-by: egemih@chromium.org Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3 Reviewed-on: https://review.coreboot.org/22517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-17amd/gardenia: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21854 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelistKevin Keijzer
TESTED on Lenovo T500 Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17mb/lenovo/t400: Add LTN154X3-L02 to list of known displaysKevin Keijzer
TESTED on Lenovo T500 Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22475 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-15variants/kahlee: Add thermal ASLMarc Jones
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15google/kahlee: Get power plug notification from the ECMarc Jones
Set the EC SCI reporting mask to include the power plug reporting. BUG=b:65637324 TEST=Check power_supply_info on AC/DC. Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-14mb/google/eve: Add DSP calibration clock name/rate for RT5514Cheng-Yi Chiang
Add a property for DSP calibration clock name and rate such that RT5514 codec driver can control ssp1_mclk for DSP clock calibration. BUG=b:67763576 TEST=boot on eve check RT5514 codec driver can get this device property. Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31 Original-Reviewed-on: https://chromium-review.googlesource.com/756261 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Set DSP SPI clock to 12MHzDuncan Laurie
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable VMXDuncan Laurie
This feature was enabled at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. Since we want this enabled anyway just set it this way in the BIOS so it matches what the kernel expects. BUG=b:68666100 TEST=pass firmware_FWtries on Eve with R63 OS image Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/749733 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Tune I2C4 hold timesDuncan Laurie
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz. BUG=b:67029862 TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/739841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable AER and LTRFurquan Shaikh
AER and LTR must be enabled individually on ports that need it, in this case it should be enabled for WiFi and NVMe. BUG=b:65457528 TEST=Wifi team verified that the performance is better with these changes. Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/671211 Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Use rt5663 driver and set propertiesDuncan Laurie
Use the rt5663 driver and provide values for the offsets which are needed for providing manual values to compensate the DC offset for L and R channels between headphone and headset. BUG=b:62712227 TEST=build and boot on eve and ensure rt5663 is functional. Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611606 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org> Reviewed-on: https://review.coreboot.org/22446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Remove ACPI control of touchscreen powerDuncan Laurie
Change the touchscreen power control back to coreboot instead of under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L pin back to an output. This reverts previous changes to touchscreen GPIOs that were made to get back to a known good/working state. Having ACPI control these pins was resulting in a small percentage of touchscreen not being discovered at boot. This platform is not intending to use S0ix so the ACPI control is not needed. BUG=b:63718744 TEST=manual testing on Eve devices. Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/572692 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22445 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/amd/gardenia: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14mb/google/kahlee: Remove direct AGESA header includesMartin Roth
All Stoney AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build and boot tested Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Add getter function for GPIO arrayMartin Roth
Instead of getting the address of the GPIO function with an extern, add a getter function and make the GPIO arrays static. TEST=Build Grunt; Build & boot Kahlee BUG=b:69164070 Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Remove mainboard.hMartin Roth
mainboard.h only had a single function definition. Move it into baseboard/variants.h and get rid of the file. TEST=Build grunt/kahlee BUG=b:69164070 Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth
Update common files and add files for grunt to the variant directory. BUG=b:68293392 TEST=Build only Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add baseboard frameworkMartin Roth
BUG=b:68293392 TEST=Build only Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13amd/gardenia: Add globalnvs.aslMarc Jones
Stoney Ridge ASL uses global NVS for sharing data between ACPI and SMM. Change-Id: I8f497870844da1f56ff5c3b126d5613be36a9bfb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13google/chell: add missing SPD hex filesMatt DeVillier
Several SPD hex files for chell were missing from upstream coreboot (as compared to the Chromium tree/branch), which resulted in the incorrect type and amount of RAM being reported on chell boards with > 4GB RAM. Add these missing files and their Makefile entries. TEST: boot google/chell m7/16GB config and observe correct RAM type and amount reported via dmidecode and cbmem console log. Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22402 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Use devicetree register values for UMAMarshall Dawson
Set the UMA memory size to 128 MiB. This value was empirically tested by AMD as the lowest value one could use. BUG=b:64927639 TEST=default, and 64, 128, 256, 384MB non-legacy configurations. Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21335 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Move DRAM clear override to devicetreeMarshall Dawson
Kahlee needs to keep its DRAM contents after a reset. Move this override out of the OemCustomize.c file to a devicetree register setting. Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21858 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5Ben Chan
On Astronaunt, after the system enters the S5 power state, there is a 10-second timeout before the system transitions the power state from S5 to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78 on the APL platform, remains on during that period. If the system is powered back on before going to G3, the built-in modem won't go through a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted. Keeping the modem, and indirectly the SIM, powered during a quick system power cycle may sometimes be undesirable. For instance, we would like a SIM with PIN lock enabled to require unlocking each time the system is powered on. After the SIM receives a PIN, it may remain unlocked until its next power cycle. Also, it is often desirable to power cycle the modem when the system goes through a power cycle. For instance, a user may power cycle the system to recover a wedged modem. BUG=b:68365029 TEST=Tested the following on an Astronaunt device: 1. Verify that the modem is powered on after the system boots from cold. 2. Suspend the system to S0ix. Verify that the modem remains powered on when the system is in S0ix. After the system goes back to S0, verify that the SIM with PIN lock enabled doesn't request unlocking, and the modem can quickly reconnect to a network. 3. Configure the system to suspend to S3 instead of S0ix, and then repeat (2). 4. Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2 Signed-off-by: Ben Chan <benchan@chromium.org> Reviewed-on: https://review.coreboot.org/22415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-09mainboard/google/zoombini: add dptf.asl and gpio.hNick Vaccaro
Add dptf.asl (copied from reef) to baseboard variant includes, instruct zoombini variant to use the baseboard's dptf.asl, instruct zoombini variant to use the baseboard's gpio.h. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I9aa37f5afc35dab372917a4c84ff3121ec569546 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/22381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09mainboard/google/zoombini: fix EC_SCI_GPI gpio defineNick Vaccaro
Change EC_SCI_GPI to GPE0_ESPI. BUG=b:69011806 BRANCH=master TEST=none Change-Id: I5d07bc0ef295d776635ff3a585c8de9028bd3f6a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/22380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mb/google/{poppy,nautilus,soraka}: Disable deep S3Furquan Shaikh
Poppy and variants won't be using deep S3. This change disables deep S3 option in devicetree. BUG=b:69053636 Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22378 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mb/google/fizz: Enable NIC ledsGaggery Tsai
This patch enables customized NIC leds as follows: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:65437780, b:68284778 TEST=Make sure the registers are programmed as expected and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09mainboard/google/kahlee: Move usb_oc.asl into variant/acpiMartin Roth
This compares to the acpi directory in other variants. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: I05d402995b280d6f020bc2575063dbffefa30670 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variantMartin Roth
Even though this GPIO isn't used for Kahlee, it needs to be defined so that the weak version of the variant_board_id() function can compile. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08google/fizz: add VBOOT_PHYSICAL_REC_SWITCH configShelley Chen
Now that recovery button has been enabled through cr50, we can add VBOOT_PHYSICAL_REC_SWITCH config and treat the recovery button like on any other chromebox. BUG=b:37751915, b:63893483 BRANCH=None TEST=With DUT in normal mode, boot into recovery, press ctrl+d followed by pressing the recovery button. Should successfully boot into dev mode. CQ-DEPEND=CL:737477 Change-Id: I72fb42508083295e317dd06900796dc0cda753f6 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22368 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mb/google/poppy/variants/nautilus: Enable Dialog DA7219 supportNaveen Manohar
Enable Dialog DA7219 codec i2c device and add required SSDT parameters BUG=b:68686020 TEST=With req'd driver support in kernel v4.4 verify audio on headset Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com> Reviewed-on: https://review.coreboot.org/22264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07mb/google/poppy/variants/nautilus: add nhlt supportNaveen Manohar
Nautilus board uses Dialog da7219 headset codec, Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. Removes unwanted DMIC blob pick for nautilus BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on headset and recording on headset mic Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07intel/cannonlake_rvp: Clean up GPIO programmingLijian Zhao
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4 platform, it is also critical to revisit the GPIO settings as they are different. Remove unused GPIO setting for old platform, and clean up the native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set to GPIO mode is illegal. TEST=Boot up in chromeos successfully. Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2017-11-07src/mainboard/intel/glkrvp: Fix Lid switch supportShaunak Saha
SCI trigger logic had to be inverted. This patch enables the system to wake up from S3 when lid is opened when the system is in suspend state.We are trying to match what a external EC card running ChromeEC FW is sending on the signal. TEST = Verified that system wakes up from S3 on toggling lid switch back to open state. Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mainboard/google/kahlee: Add MAINBOARD_FAMILYLann Martin
BUG=b:68865273 Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3 Signed-off-by: Lann Martin <lannm@chromium.org> Reviewed-on: https://review.coreboot.org/22359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:43:36 +0000