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2016-09-28mainboard/asus/dsbf/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I74d4ef76b8166c8567b1b855c6bc963b4312df77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16773 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-28mainboard/intel/emeraldlake2/gpio.c: Use tabs for indentsElyes HAOUAS
Change-Id: I369c2063a5e57d1fd33d3c6bf7c715c22970fc32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/intel/eagleheights/debug.c: Use tabs for indentsElyes HAOUAS
Change-Id: I4d2d876d48e018c247e7f365f7c237a4d8ced332 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16771 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/broadcom/blast: Use tabs for indentsElyes HAOUAS
Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16745 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27mainboard/msi/ms9185/resourcemap.c: Use tabs for indentsElyes HAOUAS
Change-Id: I30b5830442da65ae3ddd35e8bca67795c34e9020 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16737 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27mainboard/msi/ms9185/romstage: Use tabs for indentsElyes HAOUAS
Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indentsElyes HAOUAS
Change-Id: Ib2ab95b26c3bb1cbd58aafb1fafd1b285d6a5ba8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-26mainboards,ec: provide common declaration for mainboard_ec_init()Aaron Durbin
Add a header file to provide common declarations that the mainboards can use regarding EC init. BUG=chrome-os-partner:56677 Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16734 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-09-26mainboards/google/reef: use chromeec's ASL lid switch implementationAaron Durbin
Defer to the lid switch implementation provided by the chromeec. BUG=chrome-os-partner:56677 Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-26soc/intel/apollolake: provide power button ACPI deviceAaron Durbin
Instead of having each mainboard provide the power button, uncondtionally provide the power button ACPI device on behalf of each mainboard. BUG=chrome-os-partner:56677 Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16731 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-26mainboard/*/*/dsdt.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/*/*/mptable.c: Improve code formattingElyes HAOUAS
Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/*/*/irq_tables.c: Use tabs for indentsElyes HAOUAS
Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16729 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/lippert: Use tabs for indentsElyes HAOUAS
Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16686 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-24intel/amenia: Remove Amenia mainboardAndrey Petrov
The mainboard is not being worked on anymore, not available outside of Intel and thus has litle practical use. Remove mainboard code completely. Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16725 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-23mainboard/lippert/frontrunner-af: Use tabs for indentsElyes HAOUAS
Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/lippert/toucan-af: Use tabs for indentsElyes HAOUAS
Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/nvidia/l1_2pvv: Use tabs for indentsElyes HAOUAS
Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16687 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21google/enguarde: Adapt to current treePatrick Georgi
Some changes were made in upstream in the meantime that broke the build: - CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS - recovery_move_enabled() -> vboot_recovery_mode_enabled() - chromeos.asl was replaced by an acpi generator Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16683 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21google/enguarde: Upstream Lenovo N21 ChromebookMatt DeVillier
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-enguarde-5216.201.B commit cf1f57b [Enguarde: Adjust rx delay for norm.] TEST=built and booted Linux on enguarde with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15444 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/getac - kontron: Add space around operatorsElyes HAOUAS
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru/kevin: Decrease voltage for little cpu 1.5G to 1.15vShunqian Zheng
In kernel side we set 1.1v for 1.5G, even for coreboot RO, a higher voltage could be safer, 1.2v now seems too high. BRANCH=none BUG=chrome-os-partner:56948 TEST=bootup Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380896 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Veyron: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted Jerry Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166 Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376884 Reviewed-on: https://review.coreboot.org/16581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20google/gru: Fix up PWM regulator rangesJulius Werner
We did yet another small adjustment to the PWM regulator ranges for Kevin rev6... this patch reflects that in code. Also rewrite code and descriptions to indicate that these new ranges are not just for Kevin, but also planned to be used on Gru rev2 and any future Gru derivatives (which as I understand it is the plan, right?). BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted my rev5, for whatever that's worth... Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9 Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/379921 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16580 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Gru: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted kevin-tpm2 Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376883 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16579 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-19Revert "mainboard/google/reef: Enable cr50 TPM interrupt"Duncan Laurie
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
2016-09-19mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-20gru: Add USB 2.0 PHY tuning for KevinJulius Werner
This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck@chromium.org> Original-Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://review.coreboot.org/16265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19mainboard/google/reef: Configure WLAN as wake sourceVaibhav Shankar
This implements PRW method for WLAN and configures PCIe wake pin to generate SCI. BUG=chrome-os-partner:56483 TEST=Suspend the system into S3 or S0ix. System should resume through wake event from wifi. Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16611 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19kunimitsu: Remove incorrect dereferencing of pointerRizwan Qureshi
In spd_util.c function mainboard_get_spd_data(), spd_file can either be NULL or will point to the first byte of the SPD data, and should not be dereferenced. Change-Id: I08677976792682cc744ec509dd183eadf5e570a5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16612 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15mainboard/reef: add variant support to ASL codeAaron Durbin
There are certain board-specific options for reef variants. The big one is the DPTF settings. Rearrange the ASL files such that dsdt.asl is the main landing area. The ACPI options for Chrome EC are contained in the variant/ec.h header so the actual code #includes can just reside in dstd.asl. Since most of the mainboard specific peripherals are auto generated by the acpigen from devicetree there's no real separate need for mainboard.asl. The one thing not addressed in this CL is the notion of a variant having the Chrome EC or not (along with lid, etc). Future indirection can be provided when needed to address that requirement. BUG=chrome-os-partner:56677 Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3Fabian Kunkel
This patch disables the SataSetMaxGen2 flag. This flag is a power saving option, which forces the SATA to GEN2. Payload SeaBIOS 1.9.1, Lubuntu 16.04, Kernel 4.4. $ dmesg | grep ahci #before patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode $ dmesg | grep ahci #after patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode Change-Id: I48361190969e6d38ddb5692f5e54b016b359fbb1 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15906 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15lenovo: add ps2 spinup timeout to all H8S based boardsAlexander Couzens
The h8s needs around 3s to respond to ps2 commands Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16505 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODEWerner Zeh
In commit 4f2754c 'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode' the default operation mode of SERIRQ was changed from continuous to quiet. Set the mode to continuous for this mainboard to keep the behavior unchanged. Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15google/reef: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15intel/amenia: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-09-15kunimitsu: Add FSP 2.0 support in romstageRizwan Qureshi
Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16316 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboard/intel/amenia: Configure PERST_0 pinVaibhav Shankar
Configure PERST_0 and assign the pin in devicetree. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16350 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboards/apollolake: Set RAPL power limit PL1 value to 12W.Sumeet Pawnikar
This patch sets tuned RAPL power limit PL1 value to 12W in acpi/dptf.asl for RAPL MSR register. With PL1 as 12W for WebGL and stream case, we measured SoC power reaching upto 6W. Above 12W PL1 value, we observed that Soc power going above 6W. With PL1 as 12W, system is able to leverage full TDP capacity. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboard/google/reef: Configure PERST_0 pinVaibhav Shankar
This configures PERST_0 in devicetree. For boards without PERST_0, the pin should be disabled. For boards with PERST_0 the correct GPIO needs to be assigned. BUG=chrome-os-partner:55877 Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-13mainboard/google/reef: add MKBP EC event as SCI event.Gwendal Grignou
Add MKBP as a SCI event: the EC is then able to send events coming from the sensors. BUG=b:27849483 TEST=With EC configure to send MKBP events, check sensor information are retrieved by the kernel. Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/16594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13lenovo/t60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16405 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/bcom/winnetp680: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/bcom/winnetp680. Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/gigabyte/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/gigabyte/*. Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/asus/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 16:04:07 +0000