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2018-05-08mb/lenovo: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ic044fc074c43db683fcd85ce92a36a8c5a464a67 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/jetway: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I574d9e46ebe6993f356c3617f2e5ff21b5ef55a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/google/poppy/variants/atlas: update DMIC NHLT configurationSathyanarayana Nujella
From coreboot side, include DMIC 4ch NHLT configuration and its DMIC blob. In OS side, cras picks the needed channels using UCM's channel map configuration. So, this patch updates to include DMIC 4ch config. BUG=b:79158926 TEST=Verified 4-ch record with arecord TEST=Also verified internal mic record with cras using 'cras_test_client --capture_file dmic.raw --rate 48000 --num_channels 2 --duration 10' Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google/eve: Change rt5663 audio codec's irq as ExclusiveAndWakeHarsha Priya
This patch uses GPIO macro to define rt5663 headset codec's irq as ExclusiveAndWake. This change allows jack detection even when device is in D3 state. TEST=Plug in/out jack when the system is in deep sleep and wake up the system to ensure that jack insertion/removal is detected. Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26016 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/roda: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I0830e5519256122e3fe9f142c4c8e1e5e85f9a8c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/kontron: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iac341f592acd777fe9ba22cfbca19d4cbdb4916e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/lippert: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I9a51ff76bc4fcd6ca659229c87cd7dd5bf83b43b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/pcengines: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8a05bb00dc640fafa1c8e2eaac6427fdb0169f39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/apple: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I14d82b0463d184ae89d7137f2dc6732bbb608b73 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/gigabyte: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I37ba054022241c93c03e6c804e46f4e8a1c1143e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08purism/librem13v1: Fix space->tabs and disable ME pci deviceYouness Alaoui
Change-Id: I7ffcea7bff988d3d4269e1334fc938932aed2eb4 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-08purism/librem13v1: Disable PCI Express AER capabilityYouness Alaoui
The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08src/mainboard: Set ACPI OEM ID values to 6 characters longMartin Roth
Change OEM ID values to 6 characters to fix error compiling with IASL version 20180427. Also update table creator to 8 characters from 7. Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-07mb/google/poppy/variants/nami: Invert polarity of EMR_GARAGE_DET#Shelley Chen
This gpio should be active low, but is not currently configured that way. Changing gpio configuration to reflect that. BUG=b:73121017, b:77941823 BRANCH=None TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen is ejected, gpio is low and when pen is inserted, gpio is high. Also tested that wake upon pen eject is working. Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26017 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-07mb/msi: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I7f29fe3b85bc56ff3f2d225822c415513e961459 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2018-05-07mb/winent: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ice673efd52e414e4064734883ca92dce5fc059cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26093 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-07mb/sunw: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I348a7ad368cf5b5a7837c45038a1659a581c518f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2018-05-05mainboard/ocp/wedge100s: Initial commitDavid Hendricks
This patch does the following: 1. Copy src/mainboard/intel/camelbackmountain_fsp to src/mainboard/ocp/wedge100s. 2. Update Kconfig files 3. Add board.fmd 4. Enable VPD The OCP Wedge100S is a 100GbE top-of-rack switch with a Xeon D-1500 com-express module. More info is available at http://www.opencompute.org/wiki/Networking/SpecsAndDesigns. Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: Ia150b066124953c7c0abe8ea5a13e4131194ea00 Reviewed-on: https://review.coreboot.org/25671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-05mainboard/ocp/monolake: Initial commitDavid Hendricks
This patch does the following: 1. Copies mainboard/intel/camelback_fsp to mainboard/ocp/monolake 2. Adds Kconfig files to mainboard/ocp 3. Makes minor board-specific changes (board_info.txt, Kconfig variables) The OCP Mono Lake platform consists of up to 4 single-socket Xeon D-1500 microservers in a Yosemite v1 chassis. More info is available at http://www.opencompute.org/wiki/Server/SpecsAndDesigns. Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: If358162abe67e9411fd2514d48f3b3411da15f68 Reviewed-on: https://review.coreboot.org/25669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-04mainboard/hp/dl145_g1: Remove commented codeElyes HAOUAS
Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04mainboard/google/kahlee: Pass oscout system clk to da7219Akshu Agrawal
Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04google/kahlee: Revert "Resume on AC insertion"Martin Roth
This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03mainboard/winent: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/msi/ms9185: Fix coding style and remove commented codeElyes HAOUAS
Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/hp/dl145_g1: Fix coding styleElyes HAOUAS
Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/google/reef: Remove tablet mode switch supportMartin Roth
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't exist in the apollo lake code. Remove it from reef as part of the cleanup to update to the new version of IASL. This was in commit 4f803ac28f4 (mainboards/google/reef: Add support for tablet mode switch.) Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02google/kahlee: Set SPI 100 MHz and SPI Dual Read IO modeMarc Jones
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/google/poppy/variants/nami: Enable touchscreen through ACPIShelley Chen
Currently, we've set TOUCHSCREEN_DIS gpio to disabled. Enabling through ACPI. Set reset/enable/stop_off_ms variables to get timings of power off sequence correct. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib1543f41f24cbe8c33aeb02e6aa43fd3dd977ed4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-02mb/sapphire/pureplatinumh61: Use custom SPI OPMENUNicola Corna
The SPI chip in this board needs a custom OPMENU, otherwise flashrom fails halfway during the write. From the default OPMENU, Block Erase (0xd8) has been replaced by AAI write (0xad) and Fast Read (0x0b) by Write Disable (0x04). Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-02mb/lenovo/x201: Add Lenvovo X201i to the list of X201 variantsMatthias Gazzari
The X201 coreboot image is working well on the X201i. Besides, the X201i seems to be almost identical to the X201 except for the CPU. Change-Id: Iecc84faf78e7de34fb1add63c20904a5a28c5e9b Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-02mb/google/octopus: Configure pins to reflect delta w.r.t yorpShamile Khan
Changes in pin usage between yorp and bip - LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66 - I2S0 interface is not used in bip. It was used in yorp for DMIC Wake on Voice through Nuvoton EC. Also fix both bip and yorp pin settings for LTE_OFF_ODL (Enable LTE and add an internal pull up). Internal pull up can be removed later when sub-board (which will have an external pull up for this signal) is available. BUG=b:77869623 BRANCH=none TEST=Build coreboot for octopus. Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01asrock/b75pro3-m: fix the HDMI portIru Cai
At the time I ported coreboot to this board, the HDMI port of my board was broken, so I couldn't test libgfxinit on HDMI. Change-Id: Ibb8a4ef55bd97fd2d0baacdbc72863c0985d3d76 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/25820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-01mb/google/poppy: Add variant for nocturneNick Vaccaro
Add a new variant of poppy for the nocturne board. Key differences from baseboard include: - GPIO changes - devicetree.cb changes - memory stuffing option changes BUG=b:78122599 BRANCH=none TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I11c7829041b3c45407c17f71b08cc7fc17f717e8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01mb/google/poppy/variants/nami: Enable Synaptics touchpadivy_jian
BUG=b:74595037 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: PNP0C50:00 06CB:CD84 Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Signed-off-by: ivy_jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
This change also makes sure that the sum the uma regions (TSEG, GSM, GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between 2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR setup for ramstage. At least tianocore requires this and fails to boot without it. Better MTRR are achieved by making the memory 'hole' till 4GiB exactly 2Gib. This code mimics how it is done in nb/intel/gm45 and achieves similar results. TSEG is enabled and set to 8M since this makes it easier to reuse the common smm setup / parallel mp code and makes it possible to cache the ramstage in there like how it's done on newer targets. TESTED on Intel DG43GT. Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-01mainboard/hp/dl145_g3: Fix coding styleElyes HAOUAS
Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23532 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30mb/lenovo/x220: Allow optional use of the mrc.binArthur Heymans
Besides the FSP codepath, Sandy Bridge has two codepaths, one native and one in the form of a binary. This allows the use of the binary. This can be useful to find flaws in the native raminit. The native raminit is still selected by default. Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-30asrock/b75pro3-m: use the ASPM blacklist driverIru Cai
After commit 2188f57a (src/device: Update LTR configuration scheme) coreboot will hang when reading resources on the ASMedia SATA controller, although there is already an ASPM config override. So use the ASPM blacklist driver instead of setting the ASPM override in the devicetree. Change-Id: I807d9bd4deef8c1528dff96c7646240ef75e1953 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/25819 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30google/poppy: enable trackpad as wake sourceCaveh Jalali
This configures GPP_A23 as a wake source for the trackpad. We also need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any interesting signals in GPP_B, so we won't be missing it. I don't have hardware with A23 wired up, so i just tested the wake source using A19 which is essentially identical to A23. BUG=b:78541883 TEST=verified we can trackpad can wake system from suspend Change-Id: If800464c8b2319d758b1823850571919f85bdc6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30cubieboard/qemu-armv7/am335x: Add fake TTB region for consistencyJulius Werner
All ARM architecture boards are supposed to have a TTB region for their page tables. ARM systems cannot use the data cache without enabling paging, so it is imperative to do that as soon as possible. They will also fault on unaligned accesses when not using the cache, which breaks assumptions in CBFS code. Unfortunately, we have some old boards in various stages of disrepair in the tree that don't always follow these sorts of standard conventions. It's not clear whether they actually boot anymore and if anyone still has the respective hardware available to maintain them. I cannot really fix and test them right now, but we should at least create a fake TTB section for them so that common architecture code may make the correct assumptions about which regions exist. Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30mb/google/octopus: Create phaser variantJustin TerAvest
This creates a phaser variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:78572180 TEST=None Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30mb/google/octopus: save dimm info as SMBIOS Table-17Ravi Sarawadi
Save FSP provided memory HOB info as SMBIOS Table-17 format. Firmware tools such as mosys, dmidecode uses SMBIOS Table-17 to report memory metadata. BUG=b:78651920 TEST=Build for Octopus and check 'dmidecode -t17' and 'mosys memory spd print all' to verify dimm info. Change-Id: I9b032b766a2927725b2378f7f720644d4459f602 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/25881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30mb/google/octopus: Fix crossystem wpsw_cur errorHannah Williams
With only one entry for Write Protect gpio in the OIPG package, the sysfs entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO" instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur. BUG=b:78009842 Change-Id: Ica60f342420d95d09a45580f2f940443c03601de Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-29pcengines/apu2: remove TPM from devicetree for apu3Piotr Król
There is no physical LPC connector on apu3 mainboard. This board contains only LPC debug test points with not all required pins exposed. Change-Id: I83de16bb651846340788c6fa52c04b8e09e46a99 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/22630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-29mainboard/amd/olivehillplus: Fix coding styleElyes HAOUAS
Change-Id: I489780d205e0784914063454c6071b046df6cc30 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:09:00 +0000