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Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7201
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7200
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7238
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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cpu/intel/romstage.h is needed so the the main() has a
prototype in freestanding.
Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7235
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.
Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7279
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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That takes them out of .data
Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7313
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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Breaks abuild and is dependent on WIP, is WIP itself.
This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43.
Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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This is based on LENOVO X230 port. Board boots to linux via SATA.
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration.
I suggest altering the native raminit code so that it reboots
if that message appears to give a chance for the boot process to recover.
2. VGA does not work.
Native graphics initialization only supports LVDS and the
VGA Option ROM still hangs when run in SeaBIOS
3. USB does not work.
SeaBIOS/GRUB2 do not detect devices connected to USB ports
4. Sound needs corrected codec verb settings
Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7020
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I37c302c7a17645f55d568c1a5f7bb791319ddbb4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7286
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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Change-Id: Ieee54e28641f88497503d6d91ddeb52ad091d78d
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7274
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot
port to this board however used the driver of the Winbond W83627HF SuperIO,
which is compatible enough to get most stuff working, but which clears bit 6 in
register 0x2B. This switches the function of pin 38 of the NCT5572D from
RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the
unpopulated miniPCIe slot are connected to this pin, so they didn't get reset
during a reboot.
Using the newly added driver for the Nuvoton NCT5572D fixes this problem.
There is also a trace from the pin 37 of the SuperIO, which can be configured
as RSTOUT2#, to pin 82 of the USB3-chip with unknown function.
As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB
but not in Linux.
Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6266
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Minnowboard Max was broken by
commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI
because TSEG wasn't set to 8MB by the FSP.
The default in the FSP is 1MB.
Change-Id: I2e671a6ca0240e931399920c62439c36133789aa
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7240
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7231
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Id5c5d68048169b0cd400926cead2d1835194d1a5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Ibbcdbb44c7586ac8d445870789647f8ff9585452
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7232
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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With following settings
1.Coreboot 25Mhz
2.Maxim codec configured with MCLK=25Mhz
2.I2C 400Khz fixed
4.Including Enable/Disable SHDN bit when LRCLK starts/Stops
5.Removed PLL toggle workaround routine.
audio playing is smooth before/after S3, no noise when recording so change
MCLK from 19.2 back to 25Mhz.
BUG=chrome-os-partner:26948
BRANCH=firmware-rambi-5216
TEST=test audio play and record on Rambi, works fine.
Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193881
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7219
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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We're no longer configuring hotplug + backlight settings from
devicetree, so remove these entries + fields.
BUG=chrome-os-partner:27304
TEST=Compile only.
BRANCH=rambi+squawks
Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193831
(cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7218
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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bit: 7 6 5 4 3 2 1 0
LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT
so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV).
BUG=chrome-os-partner:26365
BUG=chrome-os-partner:27505
BRANCH=rambi
TEST=Booted with and without HDMI connected monitor. DEV screen
always showed on eDP panel on Rambi.
Change-Id: I8f876e78383424f517689eb25e9229a27739957b
Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675
Signed-off-by: Kein Yuan <kein.yuan@intle.com>
Reviewed-on: https://chromium-review.googlesource.com/193303
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7216
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7203
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ia4060831236d72f880eeff6263ada40cf195fb12
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7180
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Change-Id: I0ace5f49b84170ab4701ad1b70d3c50c99066e53
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Part number is used only for coreboot ROM identification and
in coreboot tables. Rather than guessing the P/N, just use readable name.
SMBIOS uses information from EEPROM and so isn't affected.
Change-Id: I33534c3acb83f20d5b493c82bfc98896bf64ff1a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7177
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Change-Id: I88e889efe43b32e7efc59ea40d13e79209a27264
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7179
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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The simo board with console output at UART port 1 (COM2) will not produce
any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly.
Commit f29200240e428761827ab8d179fa23068bfa9d59
(superio/ite/*: Factor out generic romstage component)
will only and always activate UART port 0 unregarded to
CONFIG_UART_FOR_CONSOLE value.
Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE
will be enabled and used for console output
Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: http://review.coreboot.org/7060
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I54955fa44d126b7a3d382f57b4aa0dac01688104
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7129
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7127
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I5cf6dbab64f3eda02e6418be65f21e28ddf0d9ff
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7125
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I3badb18839773e38834de967a51c29a306975d20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7152
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I242664032d368794d828fce73a20f75ded45051d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7151
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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These functions are only used for ramstage.
Change-Id: I089230ca625037637c7af061b0939fd981dbdfd2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7148
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Regression introduced with commit
7b23ae0 AGESA: Trace execution with AGESAWRAPPER()
As the call is made before console_init() is called it must
not call any printk(). Debugging Olivehill and Parmer platforms
using a custom FPGA (as these boards have no Super-IO UART) have
been observed to halt and/or delay at early boot.
Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7059
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
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Change-Id: Iddd4d99af7e1c70384f13f18d785f491c47c7617
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6712
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU
Reviewed-on: https://chromium-review.googlesource.com/183939
(cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1)
nyan_big: Add initial 792MHz BCT
Reviewed-on: https://chromium-review.googlesource.com/183975
(cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a)
nyan_big: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/184076
(cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716)
tegra124: support tri-state Board Id
Reviewed-on: https://chromium-review.googlesource.com/183855
(cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4)
nyan*: Fix SPI pinmux configuration
Reviewed-on: https://chromium-review.googlesource.com/184281
(cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489)
nyan_big: Add 4GB 204/792MHz BCTs
Reviewed-on: https://chromium-review.googlesource.com/184159
(cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e)
tegra124: Add function for obtaining DRAM size via MC regs
Reviewed-on: https://chromium-review.googlesource.com/184535
(cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48)
tegra124/nyan*: Obtain DRAM size dynamically
Reviewed-on: https://chromium-review.googlesource.com/184431
(cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3)
tegra124: Rearrange iRAM layout to allow more space for romstage
Reviewed-on: https://chromium-review.googlesource.com/184240
(cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc)
tegra124: Fix MemoryType field name in SDRAM parameters.
Reviewed-on: https://chromium-review.googlesource.com/185113
(cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97)
nyan_big: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/183624
(cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70)
tegra124: move FB_SIZE_MB to a more appropriate location
Reviewed-on: https://chromium-review.googlesource.com/184930
(cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc)
nyan: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/185114
(cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b)
tegra124: Save SDRAM parameters to PMC registers for LP0
Reviewed-on: https://chromium-review.googlesource.com/182928
(cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86)
tegra124: Rewrite SDRAM parameter saving code to be more efficient
Reviewed-on: https://chromium-review.googlesource.com/184388
(cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6)
nyan: Slightly change the way SDRAM parameter files are set up
Reviewed-on: https://chromium-review.googlesource.com/185286
(cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d)
Squashed 16 commits for SDRAM support on nyan and nyan_big.
Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6949
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)
baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)
baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)
baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)
rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)
baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)
rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)
baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)
baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)
rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)
baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)
baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)
rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)
Squashed 13 commits for baytrail/rambi.
Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ic9734bf2672942a09f2136b0c066f2eda58486d9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7126
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iee581183f9cd9f5fecd5604536b735f6a04a0f93
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7019
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Change-Id: Ic8472745c2ff0c68fd63b51d1a149a11be1650e9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7115
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7114
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove northbridge specific callouts for AGESA_READ_SPD.
Move low-level SMBus code to southbridge.
Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Remove northbridge specific callouts for AGESA_READ_SPD.
Move low-level SMBus code to southbridge.
Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7112
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: If5c62b868c4144845d79dc26068c500ab5d26947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7111
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.
Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Change-Id: Ie8e4fffcec308d1cd5e696605e78671f3ababf40
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ia3f6691ae7c33b5e22010e25a1f01996a594196e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6943
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I00d0d0e2556d4cd0553a2b3351ace26bf747ff6a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6944
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Just took combined sandybridge per-device ACPI patch and applied it
on FSP flavour to avoid need of separate tests.
Change-Id: I09838cc01ede504416078edcb1c267a11539e714
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6811
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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