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2016-11-24Add Haswell Chromeboxes/Chromebase using variant board schemeMatt DeVillier
Combine existing board google/panther with new ChromeOS devices mccloud, monroe, tricky, and zako, using their common reference board (beltino) as a base. Chromium sources used: firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...] firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.] firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...] firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...] Existing google/panther board will be removed in a subsequent commit. Variant setup modeled after google/reef Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17329 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-24Remove board google/pantherMatt DeVillier
Once #17329 is committed, no reason to have google/panther exist as a separate board anymore. Change-Id: I9a11273c39423d5ff33a7d1f91c8d8cffef97ec1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-11-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:57, critical point:90 TSR1 passive point:55, critial point:70 TSR2 passive point:65, critial point:80 2. Update DPTF TRT Sample Period. CPU: 5s TSR0: 50s TSR1: 55s TSR2: 120s BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23veyron_*: Remove obsolete ChromeboxesDavid Hendricks
This removes brain, danger, emile, and romy from the tree. This was cherry-picked from the chromeos-2016.02 branch (CL:345574), but conflicts showed up in many files that were to be deleted anyway possibly due to some widespread refactoring that was done between then and now. BUG=chromium:612660 BRANCH=none TEST=none Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73 Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412424 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17569 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-11-22mainboard/ms7721: Add MSI MS-7721 (FM2-A57MA-E35)Renze Nicolai
Adds support for the MSI MS-7721 (FM2-A75MA-E35) motherboard. Tested by building coreboot with: - VGA bios (needed for onboard video) - XHCI firmware - SeaBIOS payload CPU: AMD A8-6500 APU RAM: 2x 2GB Samsung M378B5673EH1 Confirmed booting using: - USB stick with Arch Linux (kernel 4.7.5) - Gentoo live CD from SATA dvd drive - Gentoo installation from SATA harddisk (kernel 4.4.26) Change-Id: I757e011de01ca9f340fd524b10e7fa3f291d53e3 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/17495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721".Renze Nicolai
This patch adds a copy of the Asus F2A85-M code with only minimal changes. (to ensure that the code compiles) A second commit will be published to remove the copied code parts that don't apply to the MS-7221 and to make everything else actually work on the MS-7221 board. Change-Id: I1426c0876c7bfeb264231c0d338301133c721484 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/17494 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22intel FSP sandy/ivy: Move select MMCONF_SUPPORTKyösti Mälkki
Note: Platforms have no MMCONF_SUPPORT_DEFAULT. Change-Id: I8a02ea78957fca23b1cf161a00d5e3edda73d683 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17543 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22mb/gigabyte/ga-g41m-es2l: Add MAX_CPU = 4 in KconfigArthur Heymans
This motherboard support Intel core 2 quads. Before this change SeaBIOS was not usable, due to it crashing before it got to load anything. Change-Id: Ifdaaceace04f9ba0753aab2d3b05c0519367f91f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17537 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-21mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPIArthur Heymans
Obtained from vendor bios DSDT, under "Device (HUB0), Name (_ADR, 0x001E0000)". The schematics also indicate that the INTA-D are hardwired to these PIRQ lines. Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17099 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21lenovo/x200/board_info.txt: Add SOIC-8 to ROM packageMichał Masłowski
Some X200 use a 4 MiB SOIC-8 flash chip. Change-Id: Ie5bd359ef08cf1be369a026be376c21555d0ea18 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: https://review.coreboot.org/8391 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-21mb/siemens/sitemp_g1p1/cmos.layout: Re-add cmos_defaults_loadedNico Huber
I guess it was dropped because its concept was misunderstood. The idea is to always have it set to `Yes` in the cmos.default. Users can then ack the loading of the defaults by setting it to `No`. If the defaults ever get loaded again, they'll be notified by the default `Yes`. Change-Id: I1aa6d75bd5aa153c7b11a6b74564272eaa7cc523 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17355 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-20intel sandy/ivy: Improve DIMM replacement detectionKyösti Mälkki
When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-11-20mainboard/google/reef: Update DPTF parameters provided from thermal teamTim Chen
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:61 TSR0 passive point:120, critial point:125 TSR1 passive point:46, critial point:75 TSR2 passive point:100, critial point:125 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min to 8W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 80secs Change CPU Effect on Temp Sensor 0 sample rate to 120secs The TRT of TCHG is TSR1, but real sensor is TSR2. Change Charger Effect on Temp Sensor 2 sample rate to 120secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18ec/lenovo/h8: Add USB Always OnNicola Corna
USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the ThinkPads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). For some reasons the "AC only" mode doesn't work, so it has been disabled. Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/17252 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-17google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:100, critical point:105 TSR1 passive point:48, critial point:65 TSR2 passive point:85, critial point:100 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min and max to 8W 3. Change thermal relationship table (TRT) setting. The TRT of TCHG is TSR1, but real sensor is TSR2. BRANCH=master BUG=none TEST= Compiled, verified by thermal team. Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: disable unused devicesJagadish Krishnamoorthy
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=chrome-os-partner:59880 TEST=Boot to OS and lspci command should not list the above disabled devices. Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/17441 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17mb/intel/kblrvp: Remove unused configs in KconfigNaresh G Solanki
Remove unused drivers & nhlt in Kconfig. Change-Id: Ic1e8a98a77a0061e749019665f955b921f85975e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: set i2c bus timings by rise/fall timesAaron Durbin
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58889,chrome-os-partner:59565 Change-Id: I0c84658471d90309cdbb850e3128ae01780633af Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17397 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-17google/gru: Move to one CA training patternDerek Basehore
This changes memory to only do CA training with one pattern, 0xfffff/0x00000 and to also make sure CA training waits for all of the captures during training. BRANCH=none BUG=chrome-os-partner:56940 TEST=boot kevin and run stressapptest -M 1500 -s 1000 Change-Id: I0982674b4f4415f4d7865923ced93fa09bdd877e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75cdd911cea9c4e5744fd04505b260fa5755513c Original-Change-Id: I3b86e6d4662c6fbbf9ddef274fce191a367904e5 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/410320 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17383 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/gru: Add new CA training patternDerek Basehore
This adds a new CA training pattern for all of the supported frequencies. This pattern increases the hold time on CA. BRANCH=none BUG=chrome-os-partner:57845 TEST=boot kevin and run: while true; do sleep 0.1; memtester 500K 1 > /dev/null; done for several hours Change-Id: Ie5958cf67c16247ef90ee261da9faef4ffa5b339 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8babeafe75bffcb2dab17eb007b4f5bb0eb42606 Original-Change-Id: I7f7652f88e43dc9b2f6069e60514931bf7582ed1 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/403547 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17382 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17google/oak: Add more DRAM modules supportPH Hsu
Add support for following 3 modules. - Micro MT52L256M32D1PF / MT52L512M32D2PF - Hynix H9CCNNNBJTALAR Hana EVT was planed to add 4 DRAM modules but RAM_CODE=5 is not used in the end. This patch also unifies the naming of the RAM configurations. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: I7dd44525de8e9dde01f210f4730fa8ccd4baef21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dccd68149bcfd6fd0a83e310d43063bab645691 Original-Change-Id: I7c245c8c24be159e152f4f3cca25bf970b58425c Original-Signed-off-by: Milton Chiang <milton.chiang@mediatek.com> Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402888 Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Paris Yeh <pyeh@chromium.org> Reviewed-on: https://review.coreboot.org/17381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-16mb/ga-945gcm-s2l: Clean up SuperioArthur Heymans
GPIO register at offset 0xfc (VID Input Register) is read-only but writing 1 to bit 0 will update initial VID input. Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17412 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16google/eve: Fill out memory ID tableDuncan Laurie
Add the DIMM SPD data for memory types that are not used yet but are on the matrix and may be used in future builds. Also fix a typo in the part number string for one type. BUG=chrome-os-partner:58666 TEST=build and boot on eve p0 Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-15mainboard/via/vt8454c: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/vt8454c. Change-Id: I94e22e1d814733c4049e78e5b3c23b9bb429f6fa Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17312 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-m700: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-m700. Change-Id: I7a16a9f396d50279cf2bd13de72bd78e8f53f7d8 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17311 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/via/epia-cn: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/via/epia-cn. Change-Id: I1b05abcedc427e4876e1fdab85298015308a3d17 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17310 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15mainboard/tyan/s8226: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/tyan/s8226. Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17309 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15google/link/i915.c: Fix build error when native gfx init enabledIru Cai
- Move members of struct edid to struct edid_mode - Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/17332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-14google/chell : update DPTF policy settingsSumeet Pawnikar
Fine tuned DPTF policy values for chell device as below, 1. Increase Passive temperature value to 52 degree Celsius for TSR2. 2. Remove charger effect for TSR2. 3. Increase Minimum PowerLimit1 to 3W. 4. Reduce Maximum PowerLimit1 to 6W. BUG=chrome-os-partner:54718 BRANCH=None. TEST=Built for chell device. Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14intel/kblrvp: Enable TPMNaresh G Solanki
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support. Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb. Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-11samsung/stumpy: fix power LED operationMatt DeVillier
commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API] broke power LED operation when it incorrectly transferred values from the old function (it8772f_gpio_setup) to the new one ( it8772f_gpio_led). Restore the correct values so power LED illuminates when powered on. Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17266 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-11mainboard/google/snappy: Configure PERST pinWisley Chen
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11kblrvp: Add support for Hynix memoryNaresh G Solanki
Add support for hynix memory variant of RVP3. Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/intel/kblrvp: Add support to read board ID from ECAamir Bohra
Add a function to identify an Intel RVP board by querying EC Change-Id: I21337000827639fb8f22c5ee9bc5d86f1ebe1e74 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/17283 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11google/snappy: update timing of sdmode togglingWisley Chen
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17361 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/google/snappy: Set PL1 override to 12000mWWisley Chen
Snappy is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-10mainboard/google/reef: Add digitizer device to devicetreeFurquan Shaikh
BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified kernel is able to talk to the device. Even without the digitizer, no issues observed with the kernel. Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10mainboard/google/reef: Tune digitizer I2C frequency to 400kHzFurquan Shaikh
This brings the I2C frequency down to 400kHz which is spec for fast I2C. BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified frequency in kernel. Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17342 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10drivers/i2c/wacom: Make the driver more genericFurquan Shaikh
Wacom I2C driver can be used by devices other than touchscreen. e.g. digitizer. So there is no need to name the driver with touchscreen specific attributes. Only a separate descriptor name is required that needs to be set by mainboard correctly. BUG=chrome-os-partner:56246 BRANCH=None TEST=Compiles successfully. Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17341 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10intel/kblrvp: Program I/O expanderNaresh G Solanki
Program I/O expander connected on I2C bus 4 Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/thomson/ip1000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/thomson/ip1000. Change-Id: Id7b979d2539d4a80609a60464527939c4d449822 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17308 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/supermicro/h8qme_fam10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/supermicro/h8qme_fam10. Change-Id: Ia03c205ce498eadf8a34749a6a21fb2d0b29c840 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/supermicro/h8qgi: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/supermicro/h8qgi. Change-Id: I6cf123272283edbf89e854e4aa1a15a2d566133e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/roda/rk9: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk9. Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17302 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/roda/rk886ex: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk886ex. Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 01:22:00 +0000