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2014-12-31ipq8064/storm: UART enable and various fixesVadim Bendebury
The original patch from chromium was a bit of a mishmash. Between that, rebasing and using the coreboot.org UART infrastructure, the patch has changed a bit from the original. It seems reasonable to keep these changes together. - build in the ipq UART and turn on bootblock console - sets LPAE and ROM header address - adds cpd.c to storm The original commit: ipq8064: make UART driver work in bootblock This patch it the last one in the chain adapting the ipq9064 UART driver for use in coreboot. A new config option (CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of the driver. The previously introduced uart_wrapper.c is now included in the build to provide the console driver structure used by ramstage. Necessary configuration options are added to allow use of UART in the bootblock. BUG=chrome-os-partner:27784 TEST=with this change the coreboot image on AP148 prints a banner on start up: coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting... Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196663 (cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91 Reviewed-on: http://review.coreboot.org/7875 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-31nyan*: Set GEN2 I2C pads to open-drain modeKen Chang
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus the pinmux E_OD bit of these two pins needs to be set to ensure GEN2 I2C pads work fine on 3.3V. BRANCH=nyan BUG=none TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c on blaze w/o this change. the waveform looks good on both scl/sda pins w/ this change. Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200996 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea Reviewed-on: http://review.coreboot.org/7952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31rambi: Add _PRW for LID0 ACPI DeviceShawn Nematbakhsh
The kernel will not track wakeup events for devices unless they have a defined _PRW. There is no EC output of the lid signal coming to a GPIO and instead it pulses PCH_WAKE#. BUG=chrome-os-partner:27631 TEST=Manual on Rambi. - Run lidclose + lidopen on EC console, verify that wakeup_count increments. - Run lidclose + lidopen in rapid succession, verify that suspend request is aborted. BRANCH=Rambi. Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200289 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a Reviewed-on: http://review.coreboot.org/7945 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31rambi: Unconditionally clear the EC recovery requestSheng-Liang Song
Implement Rambi clear_recovery_mode_switch() BUG=chromium:279607 BRANCH=TOT TEST=Verified recovery sequences on Rambi. Original-Change-Id: I481329d0f49584ad0314bd982b80bbc86112c2c0 Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197781 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Commit-Queue: Sheng-liang Song <ssl@google.com> Original-Tested-by: Sheng-liang Song <ssl@google.com> (cherry picked from commit 77e60a039f3d8328694a743e7cd15cce71b02f5d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I837151551b8aa68cf86b6fa1dd39b7b673d6a4d9 Reviewed-on: http://review.coreboot.org/7896 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-12-30Rambi: Set SOC_DISP_ON as GPIO to avoid LCD_VCC glitchKein Yuan
To avoid LCD_VCC glitch on cold reset, set SOC_DISP_ON as GPIO output high. After gfx initialize is done, set it to native function 2. BUG=chrome-os-partner:25159 BRANCH=firmware-rambi-5216.B TEST=Tested on Rambi and squawks, no LCD_VCC glitch anymore. Original-Change-Id: If16af498e910a8da1d77a9a66456eb767286a61a Original-Change-Id: Icf62588fa0338f89fafb3fe9246c26f16bcdaa60 Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197985 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 6f7d621678f22133c9825565fedc77d19198b08c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibaf547b8d1c27811a1bec9fa3254d559c505a361 Reviewed-on: http://review.coreboot.org/7893 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-30nyan_blaze: Enable USB port2Neil Chen
There is a hub in USB port2 downstream. BUG=chrome-os-partner:28964 BRANCH=None TEST=emerge-nyan_blaze coreboot depthcharge chromeos-bootimage and verify usb port2 is workable Original-Change-Id: I0e698970729911f401f89594232f9d49e4da93cc Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200417 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 9316acfe8791585f778eecead95943e6422ca419) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I76e4331ea6e803bfbbddefab449310421c0c1d9c Reviewed-on: http://review.coreboot.org/7949 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-30nyan*: Log boot reason in eventlogDavid Hendricks
BUG=none BRANCH=nyan TEST=built and booted on Big under various modes, verified that expected boot mode showed up using "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8d98487a2cb910874c8d741008ae59a6c89102e7 Original-Reviewed-on: https://chromium-review.googlesource.com/199691 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 9f4b2574c1af23dcdc01706e9a118441f46a0f97) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibbf264a1e05323dfddb7cdb270ee6f2d49e83eff Reviewed-on: http://review.coreboot.org/7946 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-30ipq8064: prepare uart driver for use in corebootVadim Bendebury
The IO accessor wrappers are used to allow integer register addresses. A structure defining UART interface configuration is declared and defined. A few long lines are wrapped. Interface functions are renamed to match the wrapper API. cdp.c is edited to fit into coreboot compilation environment, and the only function required by the UART driver if exposed, the rest are compiled out for now. BUG=chrome-os-partner:27784 TEST=after all patches are applied the serial console on AP148 becomes operational. Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196662 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 Reviewed-on: http://review.coreboot.org/7874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30mainboard/lenovo/t530/Kconfig: No Super I/O on this boardEdward O'Callaghan
Disable Super I/O related topics showing in menuconfig. Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7985 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26blaze: change ramcode 0001/0010 to use 792MHz bctJerry Wang
This change updates the cfg file for Micron/Samsung 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/199296 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7 Reviewed-on: http://review.coreboot.org/7902 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: Detect watchdog resets and reset the whole machine.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. That puts the machine in a funny state and may prevent it from booting properly. BUG=chrome-os-partner:28559 TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/198582 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7900 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26blaze: change ramcode 0000 to use 792MHz bctKen Chang
The original sdram-hynix-2GB-792.inc was just copied from nyan bct file. This change updates the cfg file for Hynix 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197660 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec Reviewed-on: http://review.coreboot.org/7898 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: I2C: Implement bus clear when 'ARB_LOST' error occursTom Warren
This is a fix for the 'Lost arb' we're seeing on Nyan* during reboot stress testing. It occurs when we are slamming the default PMIC registers with pmic_write_reg(). Currently, I've only captured this a few times, and the bus clear seemed to work, as the PMIC writes continued (where they'd hang the system before bus clear) for a couple of regs, then it hangs hard, no messages, no 2nd lost arb, etc. So I've added code to the PMIC write function that will reset the SoC if any I2C error occurs. That seems to recover OK, i.e. on the next reboot the PMIC writes all go thru, boot is OK, kernel loads, etc. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197732 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc Reviewed-on: http://review.coreboot.org/7897 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-22hp/pavilion_m6_1035dx: Enable IOMMUAlexandru Gagniuc
Change-Id: Ia14490c9074d35b7dde99e38b4ee169d4e4589a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7678 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-20AGESA fam15tn fam15rl fam16kb: Add OemInitMid()Kyösti Mälkki
Change-Id: Icbad42168ec3afb7780c0c2ddc17aa405e08d693 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7825 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add OemCustomize hooks structureKyösti Mälkki
We should potentially provide an OEM platform hook to manipulate parameters around any entry point to AGESA. Use structure for such ops to avoid weak functions and lots of empty function stubs. Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7824 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Ignore error in OemCustomizeInitEarly()Kyösti Mälkki
It does not really matter if we continue or return after a failed assertion, system configuration is invalid anyway. Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Add amd_initenv()Kyösti Mälkki
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19qemu-armv7: Trivial style fixesDavid Hendricks
Minor style fixes to avoid future bikeshedding. - Opening brace for functions go on their own lines. - use fixed-length types where appropriate. BUG=none BRANCH=none TEST=it compiles Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: If9855d32c8ed1f5977937806c8c4cce65dd7d450 Original-Reviewed-on: https://chromium-review.googlesource.com/196955 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit e2bfeed18636af6b532e2e8f118de22a658fe41b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/mainboard/emulation/qemu-armv7/uart.c Change-Id: I8e09db53534802262168e65ec4cd47b96386490a Reviewed-on: http://review.coreboot.org/7867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19nyan*: Clear VDDIO_SDMMC3 to reset SD card reader.Hung-Te Lin
When across warm reset, if VDD_3V3_SD_CARD gets power-cycled but VDDIO_SDMMC3 does not, we will get ~1.5V leakage on VDD. To fix that, we reset VDDIO_SDMMC3 to 0 along with VDD_3V3_SD_CARD in Coreboot. Payloads must turn on VDDIO_SDMMC3 explicitly before accessing SD card. Note the warnings of "VDD_SDMMC must set early" in comment seems only happens on U-Boot and can be removed. BUG=chrome-os-partner:27053 BRNACH=nyan TEST=Ctrl-U to boot from SD card, login and type "reboot", then Ctrl-U to boot again. Without this patch, system will fail in loading kernel. Original-Change-Id: I7f85995317d18587d514ea3afcff3bfea0a33e93 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196961 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 2cfdb78d9dc229a3c06f19bbe137d59d923908a4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie7d814e0424478c35a56fbc959437ee6a555684a Reviewed-on: http://review.coreboot.org/7866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Disable SD card reader power gpio.Hung-Te Lin
When warm booting, SD card reader on Tegra 124 needs to be reset by setting power GPIO to zero. Since we don't really access SD card in Coreboot, set it to zero and let payloads enable power when they need to access SD cards. CQ-DEPEND=CL:196783 BRANCH=nyan BUG=chrome-os-partner:27053 TEST=emerge-nyan coreboot depthcharge chromeos-bootimage # With related changes in depthcharge, boots SD card successfully. Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196774 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a Reviewed-on: http://review.coreboot.org/7865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Add fast link training functionsJimmy Zhang
Some panels (including those on Big DVT) cannot work fine without link training before sending the video signals, especially multi-lane Full HD panels. We need to use the fast link training functions from kernel to support them. BRANCH=Nyan BUG=chrome-os-partner:28128, chrome-os-partner:28129 TEST=tested on nyan, nyan_big dvt. Vince verified on Full HD panels. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4 Original-Reviewed-on: https://chromium-review.googlesource.com/196162 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1 Reviewed-on: http://review.coreboot.org/7864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19gigabyte/ga-b75m-d3h: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
It is implied by DYNAMIC_CBMEM. Change-Id: I6859c4950ce568fb76c7604e9e994031a3d94d78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19beaglebone: use new arm bootblock infrastructureAlexander Couzens
8b685398 change config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: Ifac4a18a2e380c3472f51aaa7cc7842b01a2553e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7190 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19mainboard: Strip out some dead includesEdward O'Callaghan
Change-Id: I0079fa089ba863c6e447bcee3440a7e0ba0f2372 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7429 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18amd/olivehillplus/romstage.c: remove not useful variable 'halt'WANG Siyuan
The variable 'halt' is not useful and results in a compile error because of: 1b2f2a07 Introduce halt() build error: src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main': src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow] In file included from src/include/cpu/x86/lapic.h:6:0, from src/mainboard/amd/olivehillplus/romstage.c:29: src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow] cc1: all warnings being treated as errors make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1 Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7847 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18Drop VIA Epia-NStefan Reinauer
ROMCC cleanup. Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7855 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia-M series of boardsStefan Reinauer
ROMCC cleanups Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7854 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia mainboardStefan Reinauer
.. and also drop the northbridge and southbridge used by the board. This is one of the last boards to not use ROMCC for romstage. Let's get rid of it. Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7853 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-17rambi: align gpu pipea settings with the VBIOSAaron Durbin
In the normal mode case these settings aren't overwritten by the VBIOS because the VBIOS does not run. Therefore, the settings need to align with what the VBIOS programs so that there is a consistent panel power sequencing. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted. Noted settings set by firmware for both dev and normal mode match. Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196822 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf Reviewed-on: http://review.coreboot.org/7846 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17nyan*: cbmem: Move the call to cbmemc_reinit.Gabe Black
The call was after the call to vboot_verify_firmware and so would only be called when falling back to RO, aka recovery mode. This change moves it to before vboot_verify_firmware so we'll always have the cbmem console. BUG=None TEST=Built and booted on nyan and verified that the cbmem console was the same as the serial output. Built for big and blaze. BRANCH=nyan Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196158 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5 Reviewed-on: http://review.coreboot.org/7777 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: modify panel init sequenceKen Chang
Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
Enable pinmux clamp function to avoid pinmux conflict. For pins which are configured to tristate enabled, the inputs to the controller will be clamped to zero. This can be used to avoid pinmux conflicts since the tristate bit is set to 1 in the power-on-reset pinmux setting. With pinmux clamp enabled, we need to configure all the input pins to tristate disabled. BUG=chrome-os-partner:27091 BRANCH=None TEST=built and booted successfully, display worked fine. Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194060 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0 Reviewed-on: http://review.coreboot.org/7775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: Add eventlog supportDavid Hendricks
This enables event logging support for Nyan platforms. Right now this doesn't do a whole lot. We can add events in later CLs. BUG=none BRANCH=none TEST=built and booted for Nyan Rev. 1, eventlog gets initialized if necessary and can be printed by "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1 Original-Reviewed-on: https://chromium-review.googlesource.com/191200 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7 Reviewed-on: http://review.coreboot.org/7774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-16blaze: Change samsung RAMCODE to samsung-2GB-204/samsung-4GB-204Neil Chen
hynix-2GB-204MHz/hynix-4GB-204MHz are not workable with Samsung RAMCODE. To replace them by samsung-2GB-204/samsung-4GB-204 for bring up purpose. BRANCH=none BUG=chrome-os-partner:27682 TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and boot to kernel successfully with all the RAMCODE Original-Change-Id: I7c2a96e84e6988dd739a9621ff93edc01703306a Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195396 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> (cherry picked from commit dc028c408be58f036fe125abc2e49e2c0cde0aa8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieeb0250e42fb48c6089bc8dc95550c9b1694d7f8 Reviewed-on: http://review.coreboot.org/7772 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16Drop SC520 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ia70befc59708c360ad02ed7e3a49d3b0f95dc707 Reviewed-on: http://review.coreboot.org/7119 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16Drop GX1, CS5330 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
There is no need to call cbmemc_reinit() exclusively in romstage, that is done as part of the CAR migration of cbmem_recovery(). CBMEM console for romstage remains disabled for boards flagged with BROKEN_CAR_MIGRATE, but with this change it is possible to have it for ramstage. Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms. To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy. Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16i2c: Replace the i2c API.Gabe Black
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
PLLD, the clock for display, was previously hard-coded to 306MHz. To support more different panels, we should calcualte PLLD by panel pixel clock configuration. Note existing pixel clock configurations for nyan* boards won't work (they used to rely on hard-coded approximated values) so the device trees are also modified. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan_big coreboot chromeos-bootimage See panel correctly initialized and got DEV screen. Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193565 (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916 Reviewed-on: http://review.coreboot.org/7762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: pinmux: fix PWM1/2 conflictsTom Warren
GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO. Even though no problems were caused by this, correct it here so we get a conflict-free pinmux map. BUG=chrome-os-partner:27091 BRANCH=none TEST=Built and booted on Nyan, ran TegraShell "pinmux check" and saw no conflicts. Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194582 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c Reviewed-on: http://review.coreboot.org/7759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: set safe values for href_to_sync and vref_to_syncJimmy Zhang
href_to_sync and vref_to_sync are chip specific settings. Currently they are set to 1/2 of hfront_porch and vfront_porch respectively. However, to support EDID (CL192730), per David Ung, the safe values for both are 1 (the same settings as in kernel). BUG=none BRANCH=none TEST=built and booted on nyan. Original-Change-Id: Ifb8898e720a160ba044e2b526de2a4d17bc63672 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193504 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit a7128a533ba6083ddfeeca3ba0828962cc2c8ab6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6954a5b49c798ebdffb20e3ebc9099cd17591b79 Reviewed-on: http://review.coreboot.org/7758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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