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2018-08-07mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power onSeunghwan Kim
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on, it may cause damage on the GPIO pad. To prevent, we would set this pad to GPO on romstage before EDP power on. Since we need to cover all systems in market, I put it into romstage instead of early_gpio_table. BUG=b:111860510 BRANCH=poppy TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07mb/google/poppy: Add variant callback for romstage GPIO configurationFurquan Shaikh
This change adds variant callback to get GPIO configuration table in romstage and configures these GPIOs before memory training is performed. BUG=b:111860510 BRANCH=poppy Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07mb/google/poppy/variants/nautilus: Add SKU info to SMBIOSFurquan Shaikh
This change provides implementation of smbios_mainboard_sku() to add proper "skuX" string to SMBIOS table 1. BUG=b:112163362 TEST=Verified "dmidecode -t 1" reports skuX correctly. Change-Id: I7e42d2c80d791ea7170d066d2eeaa0c6811eb9c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06mainboard/google/kahlee: Add PSPP override settingMarc Jones
Add default PSPP AGESA setting for Kahlee/Grunt mainboards. BUG=b:112020107 TEST= build test Change-Id: I8a8605402379de88a04f3a16553c308513fa1531 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06google/grunt: Move PSP_SELECTABLE_SMU_FW to socRichard Spiegel
Now that an updated bootloader with important fixes is available at coreboot repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27844 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mb/google/octopus/variants/baseboard: Update Power Limit1Sumeet Pawnikar
Update power limit1 value from 8W to 10W. There is an error in the energy calculation for current VR solution on GLK. Experiments show that when power limit1 set to 10W, gained performance improvement with SoC TDP reaches max (6W) power. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/octopus/variants/fleex: Enable Weida touchscreen deviceCrystal Lin
This change adds ACPI properties for WDT8752A device. BUG=b:111402335, b:111102092 BRANCH=master TEST=Verify touchscreen on fleex works with this change Change-Id: Id186d5b87343007ae7e631d5d27464ee27e5b27d Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add rammus devicetree.cbZhuohao Lee
Use the default value for Iccmax which is specified in vr_config.c. The AcLoadline and DcLoadline keep the poppy value. Besides, the USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT and the others on the daughterboard are set to USB2_PORT_LONG. Those setting need to be fine tuned later. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add gpio settingZhuohao Lee
The gpio setting is based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add memory configurationZhuohao Lee
Add memory configuration based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add audio, mic and codec configurationZhuohao Lee
Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: change build directory to rammusZhuohao Lee
Move the build board directory from poppy to rammus. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I3a9fc2bbfe7261661f0c5c073baff0ff1434d09f Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/kahlee: Disable SATA in all boardsRichard Spiegel
Kahlee based boards don't use SATA, so disable SATA on all boards to save power. BUG=b:112139043 TEST=Build and boot grunt, checked the absence of SATA PCI. Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-05southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by defaultAngel Pons
Since only a handful of boards have descriptor blobs in the tree, it makes no sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard. This patch flips the default value of said variable, rendering all current overrides unnecessary. The few boards which have an IFD in the blobs repo use `select HAVE_IFD_BIN` to enable adding the IFD by default. Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed alongside the latter, and has been added to the boards with a ME blob as `select HAVE_ME_BIN`. Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well. Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04mb/pcengines/apu2: turn LED 2 and LED 3 off in final stageMichał Żygowski
Due to vendor's requirements LED 2 and LED 3 should be turned off in late boot process. Add appropriate functions to read and write GPIO status. Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04mb/pcengines/apu2: change GPIO settingMichał Żygowski
Change GPIO setting to use IOMUX to refer to GPIO by IOMUX register as in BKDG for Family 16h Models 30h-3fh Processor Rev 3.06. Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-03mainboard: Add ASUS P8H61-M LXTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driverMatt DeVillier
These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03mb/google/poppy/variants/atlas: Apply correct AC/DC loadlinesGaggery Tsai
This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b:111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27788 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cheza: Deassert USB hub reset pinJulius Werner
This patch makes sure we deassert the USB hub reset pin so the hub will work with the next board revision that drops the external pull-up. (Actual USB support comes in a later patch.) Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27790 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02cheza: Add board ID, RAM code and SKU IDJulius Werner
This patch adds the required callbacks to read all strapping IDs on Cheza. Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02mb/lenovo/x1_carbon_gen1: add vbtAlexander Couzens
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware. Thanks to Igor Lee. Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-02mb/google/poppy/variants/nami: Tune Fan speedSumeet Pawnikar
Tuning of fan speed for different temperature values. Earlier while running few benchmarks, fan was always getting on and starting at higher speed. With this change fan will start with lower speed and slowly speed gets increased if temperature continue going high. Thermal team provided these data after fine tuning of fan speed. BUG=None. TEST=Verified on Nami running with different benchmarks and observed fan speed. Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02mb/google/poppy/variants/nami: Enable mbox command for ISL VR c-state issueShelley Chen
There is a potential IMVP8 issue for KBL that affects Intersil VRs Nami is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:112081534 BRANCH=None TEST=Build and boot Nami Verify that suspend/resume and consecutive reboots are working Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-02google/banon: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/edgar: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 2319742 and 3b59fb2 [Edgar: Add Micron MT52L256M32D1PF-107 SPD data] [Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data] Supported 2nd source Hynix, Micron, and Nanya memory. TEST=Built and used mosys command by "mosys -k memory spd print all" Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579 Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0 Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Configure WLAN_CLKREQ as GPIO and always assert lowMatt DeVillier
Adapted from chromium commit adcb858 [cyan: Configure WLAN_CLKREQ as GPIO and always assert low] This is a workaround for issue b/35648315 as proposed by Intel to ensure that WLAN_CLKREQ always stays low. BUG=b:35648315 Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1055652 Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Tested-by: Rajat Jain <rajatja@chromium.org> Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mask Audio IRQ on bootMatt DeVillier
Adapted from chromium commit cf18ab6 [Strago: mask Audio IRQ on boot] Do not start with audio interrupt unmasked; this causes interrupt storms on newer kernels that no longer mask all interrupts when initializing Cherryview pincontrol driver. TEST=Boot various cyan boards with kernels 3.18 and 4.14; verify everything works. Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894688 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mark GpioInt() resources as PullDefaultMatt DeVillier
Adapted from chromium commit 3750e09 [Strago: mark GpioInt() resources as PullDefault] coreboot considers GPIO resources first-class citizens and initializes all pads according to their intended use, with necessary pull settings applied. Therefore let's use PullDefault as pull qualifier in AML, letting the kernel know that it should not attempt to alter pull settings when using GPIOs. TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices. Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/898259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27760 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggeredMatt DeVillier
Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: do not hardcode virtual interrupt numbersMatt DeVillier
Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02mb/google/octopus: Enable EC SW sync for allJustin TerAvest
Since this works on Yorp and Bip, we should enable EC SW sync for all known boards so that it doesn't get forgotten. BUG=None TEST=None Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27755 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01mb/google/poppy/variant/nami: Overwrite AC/DC loadlinesGaggery Tsai
This patch adds a function to overwrite AC/DC loadlines for differnt projects. BUG=b:111761175 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump AC/DC loadline settings. Tested on Vayne and Akali. Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-31mb/google/octopus: add lpddr4 skus for new memory sourcesnickchen
Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046. BUG=b:111964159 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/google/octopus: Enable EC SW sync for fleexJustin TerAvest
This never got enabled for fleex; we should enable this to make it easier to have updated EC firmware. With this commit, here's the relevant console messages: sync_one_ec: devidx=0 select_rw=4 update_ec: Updating RW(active)... Trying to locate 'ecrw' in CBFS update_ec: image len = 137580 EFS: EC is verifying updated image... send_packet: CrosEC result code 1 EFS: EC doesn't support EFS_VERIFY command vboot_hash_image: No valid hash (status=0 size=0). Compute one... print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd Trying to locate 'ecrw.hash' in CBFS sync_one_ec: jumping to EC-RW send_packet: CrosEC result code 12 EC returned from reboot after 27753us BUG=b:112038021 TEST=Successful boot after EC update via sync Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-31samsung/stumpy: Add support for libgfxinitMatt DeVillier
Add support for libgfxinit Test: boot stumpy, verify all outputs operational prior for pre-OS display Change-Id: Ia720814c2225502316de5c5e9639c67df65a2ed0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-31mainboard/google/kahlee: Update VBIOS imageRichard Spiegel
The careena board requires a different setting within VBIOS in order to pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS. CQ-DEPEND=CL:1153080 BUG=b:111673328 TEST=Verify, via SOME unspecified method, that the new vBIOS is built into the Grunt/Careena ROM files. Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27643 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/amd/gardenia: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove IMC files and functions from gardenia. BUG=b:111780177 TEST=Build gardenia Change-Id: I570b7f8e364b0c2937592590cc033d5a6c9fade0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27650 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/stout: Use new PMBASE APIPatrick Rudolph
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mb/samsung/lumpy: Use new PMBASE APIPatrick Rudolph
Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/link: Use new PMBASE APIPatrick Rudolph
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/parrot/smihandler: Use new PMBASE APIPatrick Rudolph
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mb/google/poppy/variants/atlas: Add new Nanya memory optionTim Chen
- add Nanya NT6CL256T32CM-H1 to memory strapping table BUG=b:111906760 BRANCH=none TEST=none Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30mainboard/google/nocturne: simplify camera power referencesMatt Delco
This change primarily moves the PowerResource up to a more common scope so that the _PRx references are simpler. The ^ scope modifier isn't well supported everywhere amongst OSes and drivers. Windows 10 will BSOD early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could not find the object referenced by a _PRx) with the way things are currently laid out). I've also not seen a firmware outside of coreboot that tries to reference count _ON and _OFF. Isn't it up to the OS to deference count, and whatever it tells ACPI is what should happen (i.e., on means on and off means off)? Some of the _UIDs are also duplicated. This change makes them unique. A few cosmetic changes are made so that diffing cam0.asl against cam1.asl has fewer extraneous differences. Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30google/caroline: Change debounce time for jack insertion and ejectionMatt DeVillier
Adapted from chromium commit 7633daa [caroline: Change debounce time for jack insertion and ejection] We are using max debounce time. During this time line, MICBIAS will be zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE) We need to reduce this time to below 100ms for caroline device. BUG=b:79559096 TEST=see there is no more irq before jack insertion/ejection irq complete Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1143109 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27659 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30google/kukui: Enable eMMC in bootblock.Hung-Te Lin
On kukui board, the eMMC is routed to EC for boot ROM emulation when loading bootblock, and should be set back to real eMMC as early as possible after bootblock is loaded. BUG=b:80501386 TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled. BRANCH=None Change-Id: Ifefb2e26ed048c38595907cc0875757410129828 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable FPMCU powerNick Vaccaro
Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable ec host event wakeNick Vaccaro
Enable nocturne to wake from lid attach/detach events. BUG=b:111803637 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne wakes from suspend on a lid attach/detach event. Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27649 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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