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2021-02-01drivers/security/cbnt: Fix bootblock sizeArthur Heymans
Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-01mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboardFurquan Shaikh
This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each individual board to select it. TEST=Verified that timeless build does not result in any changes. Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Drop boldar variantFurquan Shaikh
This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Change EC -> PCH wake pin to GPP_F17Boris Mittelberg
A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01Revert "mb/google/hatch/dratini: Describe the privacy_gpio"Ricardo Ribalda
This reverts commit f41645c34d8b22a3d887abd56138ae794fc2dfa5. In Dragonair, during the MP stage, one of the resistors needed for this functionality has been removed. This results in the privacy-switch not readable back by the system. BUG=b:178458332 Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocpJohnny Lin
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-01-31mb/emulation/qemu-q35: Use common MADTAngel Pons
Select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT and drop the `acpi_fill_madt` function definition, which is redundant. Tested, still boots to payload. Change-Id: I6ba448f264a478e7ef060ea1dfbf5016a310d528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-31mb/emulation/qemu-q35: Define and use MMCONF_BUS_NUMBERAngel Pons
Also refactor the machine type checks to avoid code duplication. Tested, still boots to payload with 256, 128 and 64 busses. Change-Id: Ib394ba605bbfeee75aa645e989c23034cceff348 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50025 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/amd/majolica: Add an empty bootblock function to handle GPIOZheng Bao
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/amd/majolica: Add an empty function of mainboard bootblockZheng Bao
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-30mb/intel/adlrvp: Remove unnecessary whitespaceSubrata Banik
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-29mb/emulation/qemu-q35: Consolidate host bridge definitionsAngel Pons
Move all Q35 register definitions into the q35.h header. Note that real hardware does not have EXT_TSEG_MBYTES, because it is QEMU-specific. Change-Id: I4c86ac0bb05563dee111b9b4a4a71c1c31198acd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50024 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29mb/emulation/qemu-q35: Rename headerAngel Pons
The emulated northbridge is Q35. GM35 does not exist. Tested, still boots. Change-Id: Id8e114a43b54b71087d09d143176ed94329ab7af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29mb/purism/librem_bdw: Turn comments into codeAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: Iec84fc2b43c23ea85f5cf13d9f0bace73e448c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-29mb/emulation/qemu-q35: Rename PICF to PICM in ASLKyösti Mälkki
Change-Id: I395056a164b6597b6fb3dfda0d85f9a0374cd893 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28mb/google/butterfly: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I85edf649a5170a1658fb135b797c1c6e1d2a9d70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/gizmosphere/gizmo2: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are same. Change-Id: I0a4af7ebe6114338c2e8fb5fdf39a1de2cd47138 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/gigabyte/ga-b75m-d3h: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: Ic9b7dfd786ff8e1512c8678590a1dad7c984bca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/hp/pavilion_m6_1035dx: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'Build/dsdt.dsl' are identical. Change-Id: Id48df4fa0f8e5486636292ad11b8a86e71db4b17 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46080 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/asrock/e350m1: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46154 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/hp/abm: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'Build/dsdt.dsl' are identical. Change-Id: Ie93dd1f6de1357cb3f448ed79a33b688abd91731 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/asrock/imb-a180: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/amd/thatcher: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46152 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/parmer: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/padmelon: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46148 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/biostar/a68n_5200: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/elmex/pcm205400: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I1cec4049adac74270641736709774156628b2539 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28treewide: Remove unused #includes of spi_winbond.hDaniel Gröber
We want to add some function declarations as static_testable to this header but including it in a .c file outside of tests will yield a gcc warning like: error: 'function' declared 'static' but never defined [-Werror=unused-function] It seems these includes aren't necessary anyways so we just remove them. Change-Id: I17147136579140b94728ceb1c369b1348714bc53 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-01-28mb/system76/oryp5: Fix up DSDTPatrick Georgi
We started depending on dsdt_top.asl in dsdt.asl but this newly added board wasn't adapted yet, so have it catch up. Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/emulation/qemu-q35: Solve lint-001 errorFrans Hendriks
lint-001-no-global-config-in-romstage error on D0F0_PCIEXBAR_LO. DOF0_PCIEXBAR_LO is defined in bootblock.c and romstage.c. Place D0F0_PCIEXBAR_XX in local gm35.h. BUG = N/A TEST = Build and boot QEMU x86 q35/ich9 Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2021-01-28mb/google/dedede/var/galith: Add Wifi SAR for convertiblesFrankChu
Add wifi sar for galith Using convertible mode of fw config to decide to load custom wifi sar or not. BUG=b:176206495 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chromium:2649378,chrome-internal:3559387 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0f9a7ddedef550317da4bf798317619ffd1fa979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematicsSubrata Banik
1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28mb/google/parrot: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin
Raise little CPU to 2GHz at romstage to improve boot time. BUG=b:177389446 TEST=observe boot time by `cbmem` Before: 1,062,359 us After: 907,458 us Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28mb/google/dedede/var/sasuke: Configure GPP_G7 as nativeSeunghwan Kim
Configuring GPP_G7 as NC causes SD card detection issue on sasuke. So we'd like to remove the GPP_G7 override and keep the baseboard configuration as native function (SDIO_WP). BUG=b:175831709 BRANCH=firmware-dedede-13606.B TEST=Built and verified SDR104 SD card operation on sasuke Change-Id: If73337b482f04fd263caaa6fed0e54aa87bd876e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28bayhub bh720: Factor out common HS200 init codeAngel Pons
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/google/asurada: Add config for spherionYu-Ping Wu
BUG=b:178440482 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28mb/emulation/qemu-i440fx: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46077 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/emulation/qemu-q35: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/volteer: Add GL9755 support to DrobitWayne3_Wang
Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem BUG=b:174348200 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28mb/google/zork: add MST details to trembyle devicetreeShiyu Sun
Added device hid info to the MST RTD2141b device on trembyle. BRANCH=zork BUG=b:147402710 TEST=Build and flash BIOS image, see 10EC2141 appears under /sys/bus/i2c/devices Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki
With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28mb/intel/adlrvp: Remove ClkReq assignment for RP8Subrata Banik
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required. TEST=Able to detect PCIe SD card over x1 slot. Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/intel/shadowmountain: Add flash layoutV Sowmya
This patch adds the flash layout for shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-28Revert "mb/amd/mandolin: Clean up IRQ numbers"Felix Held
This reverts commit 2a1638a9cead257115ff82b18862d506015378b2. The original commit broke Mandolin and with the revert applied, I can boot into Linux via SeaBIOS again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-19 13:51:18 +0000