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2019-11-27soc/intel/cannonlake: Disable USB2 PHY Power gatingSurendranath Gurivireddy
Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation). Issue is seen on CML platforms also. So, disable power gating for Drallion too. Add devicetree entry to set the flag to disable USB2 PHY power gating for different CNL PCH based platforms BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com> Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27google/jecht: add libgfxinit supportMatt DeVillier
Tested on Guado variant Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27google/beltino: add libgfxinit supportMatt DeVillier
Tested on Zako variant Change-Id: I433863b34731584797456eee6c2d270868a4f13f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27google/eve: add libgfxinit supportMatt DeVillier
Change-Id: Id9d9d804dfc2301b8d2186aff7be331d5ddbf18a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27google/fizz: add libgfxinit supportMatt DeVillier
Change-Id: Idd7bfa4a97770f525c3f25f04f90c4bf092e4ae1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27google/glados: add libgfxinit supportMatt DeVillier
Both linear framebuffer and vga text mode verified on chell and caroline variants Change-Id: I106e7bb761055581634176a112816be8447e6745 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Disable boards from buildKyösti Mälkki
As per the 4.11 release requirement, CAR_GLOBAL_MIGRATION=n is a mandatory feature, which most binaryPI boards lack as they use BINARYPI_LEGACY_WRAPPER. Disable all binaryPI platforms, except pcengines/apu2, from the build for the time being. If a platform does not reach POSTCAR_STAGE=y and C_ENVIRONMENT_BOOTBLOCK=y within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: Id81ab0f168034187ecf62203b5a33ac6ba49a35d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27pcengines/apu2: Switch away from BINARYPI_LEGACY_WRAPPERKrystian Hebel
Adopting the mainboard code to use hooks from state_machine.h. No post codes are changed, except for those which were explicitly sent in mainboard/romstage.c. Boot time is reduced by more than 7%, from 5.029s to 4.657s (coreboot timestamps, measured for loglevel 7). POSTCAR_STAGE is required since coreboot 4.11 release. TEST=boot PC Engines apu2 and launch Debian Linux with 4.14.50 kernel Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-25mb/samsung: remove header guards for SuperIOMatt DeVillier
SuperIO header needs to be included regardless of Kconfig option, otherwise compilation fails due to missing prototype for try_enabling_LPC47N207_uart() if DRIVERS_UART_8250IO is not set. Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-25hatch: Enable EC sync in romstageTim Wawrzynczak
Now that the EC software sync in romstage ("early EC sync") patches have landed, it's time to enable this for Hatch. BUG=none BRANCH=hatch TEST=verify EC sync runs in romstage Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCKArthur Heymans
This feature and therefore the boards using it, will be deprecated soon. Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37155 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans
Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25mb/google/octopus: disable fmap cache for all octopus devicesPatrick Georgi
Meep was just the first one to fail, but the others aren't any better. Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-23mb/google/kahlee/treeya: Set touchpad hold time to 400nsPeichao Wang
According to SI team request, need to tune I2C bus 2 data hold time more than 300ns BUG=b:144736027 TEST=build firmware and measure I2C bus 2 data hold time Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/t410: Fix I2C SPD addressPatrick Rudolph
Use correct address for second DIMM. Tested on Lenovo T410: * Both DIMMs are found and are usable Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOsShelley Chen
Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22purism/librem_skl: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v2/3/4,15v3/4 boards, verify functional display after resume from S3 when using libgfxinit. Change-Id: I6bc5dab60e3601d56dae4300efee255d7c58329d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37068 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large valuesPeter Lemenkov
Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21mb/*/*: Remove BROADWELL_DE boardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21mb/*/*: Drop FSP_BAYTRAIL supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21mb/*/*: Drop Intel Rangeley mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id38eada2d08426520261d4824990a49f8302976b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-20mb/*/*: Use proper header for pm_iowrite()Arthur Heymans
These boards don't include any from sb/amd/sb800. Change-Id: I2dbe39df6e4c5a86a0714b396bb89b03bbafd164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36987 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/*/*: Drop AMDFAM10 mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/via/epia-m850: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20purism/librem_bdw: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v1/15v2 boards, verify functional display after resume from S3 when using libgfxinit. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I44d75486da3083cd1f07ea82dc18688db84a621e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/lenovo/x201: Remove unnecessary GPIO settingsArthur Heymans
GPIO49 is strapped high, so setting it low likely increases power usage. GPIO53 is hooked to a testpad so there is no reason to set it here. Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20/mb/google/hatch: Create jinlon variantWisley Chen
Create new variant for jinlon BUG=b:144150654 TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto board Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mainboard/amd: Remove AMD Torpedo mainboardJoe Moore
This also permits removal of vc/amd/agesa/f12, as it was the only mainboard using it. That will in turn allow resolving some unique Coverity issues reported against that source. Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-19Remove google/urara mainboardJulius Werner
This board never really existed and nobody has any hardware left over for it. Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-19mb/google/octopus: Disable fmap cache for meepPatrick Georgi
By removing this code, we get approximately back to where the board was before the fmap cache feature was added, which is small enough for the Chromium OS default configuration for the board to fit into the 32KB that the bootblock can use on the chipset again. Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge/mrc: Handle P2P disabling via devicetreeNico Huber
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18sb/intel/bd82x6x: Handle enabling of GbENico Huber
The integrated GbE port is toggled via the Backed-Up Control (BUC) register. We already disable it according to the devicetree setting but never enabled it. This could lead to the confusing situation that it was disabled before (different build, vendor BIOS, etc.) but shouldn't be anymore. As we need a full reset after enabling GbE, do it in early PCH init. Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/intel/dcp847ske: Disable xHCI via devicetreeNico Huber
This is supported by generic PCH code now. Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/sapphire/pureplatinumh61: Don't write BUC and beyondNico Huber
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/samsung: Clean up LPC and IOAPIC configurationNico Huber
Don't overwrite the LPC decode config of the generic PCH code, move UART init into bootblock_mainboard_early_init() and don't enable the IOAPIC, which is already done by generic code. Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/lenovo/s230u: Don't write BUC and beyondNico Huber
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/intel/emeraldlake2: Revise early initNico Huber
Move UART initialization to bootblock_mainboard_early_init() and don't override the generic LPC decode settings. Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/hp/revolve_810_g1: Don't clear BUC and beyondNico Huber
The BUC register is actually 8 bits wide and shouldn't be bluntly cleared. Change-Id: I2ffd2d161005e839e730102b56af4f66efeb551e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/google(sandybrige): Clean up LPC and IOAPIC configurationNico Huber
Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/gigabyte/ga-b75m-d3h: Drop useless function-disable settingNico Huber
This bit is already cleared by a reset. Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16Nico Huber
This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/compulab/intense_pc: Clean PCH and super-i/o config upNico Huber
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed. Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/asus/p8h61-m*: Drop unnecessary PCH configNico Huber
The generic PCH code already sets up a superset of these decodings. Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/apple/macbookair4_2: Drop unnecessary PCH configNico Huber
mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4 things here on top of the generic PCH code: 1. Enabling LPC decoding for gameports. It seems unlikely that anything is using these ports and there is no code to support gameports. 2. Decoding of COM3 instead of COM2. What COM? 3. Premature locking of ETR3/global reset. Bad idea. 4. Disabling the GbE port in BUC. Already done by PCH code. Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18sb/intel/bd82x6x: Make the pch_enable_lpc hook optionalArthur Heymans
This also changes the name to mainboard_pch_lpc_setup to better reflect that it is an optional mainboard hook. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 08:41:43 +0000