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2017-06-07mainboard/google/poppy: Add support for ELAN deviceFurquan Shaikh
Add support for ELAN 5515 device. BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07via/epia-m700: Wrap long line in commentPaul Menzel
Wrapping the long line tries to address a warning by `checkpatch.pl`, but the line is still over 80 characters long. Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20033 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-06asus/kgpe-d16: Add video card ID for VGA BIOS namePaul Menzel
The comma-separated PCI vendor and device ID is used to associate the VGA BIOS to the video device by using it as the file name of the VGA Option ROM. Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06mb/*/*/cmos.layout: Make multibyte options byte alignedArthur Heymans
Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-05google/reef: Add coralPatrick Georgi
A new variant copied from reef. Allow override of the SKU. Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20020 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-04google/rambi: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each rambi variant has a different USB port config. Port data currently available for only candy and squawks; other variants to be added once data obtained. Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/jecht: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each jecht variant has a different USB port config. Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/auron: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each auron variant has a different USB port config. Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/slippy: populate PEI SPD data for all channelsMatt DeVillier
Since dual-channel setups use same RAM/SPD for both channels, populate spd_data[1] with same SPD data as spd_data[0], allowing info for both channels to propogate into the SBMIOS tables. Clean up calculations using SPD length to avoid repetition. Changes modeled after google/auron variants. Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-04google/parrot: make chromeos.c compilation conditional on CONFIG_CHROMEOSMatt DeVillier
No reason to compile/include chromeos.c for non-ChromeOS builds Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/lulu: enable SATA device to sleep in S0Matt DeVillier
sata_devslp_disable was set to work around some buggy SSD firmware, but as it's disabled by default in both Linux and Windows, no reason to disable at the firmware level when many properly-functioning SSDs can take advantage of power savings. Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04mb/google/poppy: Update camera sensorNaresh G Solanki
Update camera sensor detail to OV 13858 Also update i2c address of OV5670 BUG=None TEST= Build & boot to ChromeOS. Check for both the camera detection. Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-03mb/lenovo/*/cmos: Remove unused option and checksum fixPatrick Rudolph
Fix for all Sandy-Bridge and Ivy-Bridge devices. Remove unused option "hyper_threading". Increase CMOS checksum range to cover all user adjustable settings. Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-03mb/google/fizz: set SD_CDZ to edge trigger.Kane Chen
This is to align with the SD_CD GpioInt setting in acpi BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/20001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER. * Let drivers select it if they are in charge. * Don't select it on the mainboard level if a driver handles it. Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02intel/bakersport_fsp: Move into bayleybay_fsp as a variantMartin Roth
The separate directory was the old way of handling variant boards. Update bakersport_fsp to the new method. All of the other pieces were already moved into bayleybay_fsp. Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-02google/rambi: disable PCI device for unused i2c busesMatt DeVillier
Light sensor isn't used and ACPI already removed, so disable I2C5 bus interface as well. Disable I2C6 for devices without a touchscreen Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-02mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selectionAamir Bohra
Remove MONOTONIC_TIMER_MSR selection from mainboard Konfigs, as it only does a reduntant selection of HAVE_MONOTONIC_TIMER config, already selected under skylake soc Kconfig. Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20002 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02mb/intel/d410pt: Add mainboardArthur Heymans
This board is almost identical to D510MO, the only differences are some differences in populated connections, CPU with less L2 cache and a 10/100 Realtek NIC. The vendor uses the very same binary for both D510M0 and D410PT. Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-01mainboard/google/poppy: Enable H1 I2C TPMFurquan Shaikh
Enable H1 I2C TPM in Kconfig and devicetree for poppy. CQ-DEPEND=CL:513513,CL:*381534 BUG=b:36265511 BRANCH=None TEST=Compiles successfully. Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31mainboard/google/poppy: Power down camera rails when suspendingFurquan Shaikh
BUG=b:62147763 Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31google/slippy: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each slippy variant has slightly different USB port config; data for falco and leon to be added once available Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31google/beltino: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. All beltino variants use the exact same USB port layout. Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31google/parrot: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Move inclusion of mainboard.asl after southbridge asl files so scopes referenced in usb.asl are valid. Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31mb/lenovo/t430: Fix PCIe hot-plug portsPatrick Rudolph
Port 0 is connected to SD-card reader. Don't mark it as hot-plugable. Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-31mc_tcu3: Remove all hwinfo files from mainboard directoryWerner Zeh
To unify the hwinfo handling along all Siemens MC boards the hwinfo files have to be removed from the mainboard directory. They will be added to cbfs in site-local/Makefile.inc. Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-05-31mc_bdx1: Switch to RTC RX6110SAWerner Zeh
The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard. Switch to the new RTC in Kconfig and adapt devicetree to the new chip. Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-05-31mb/google/eve: Update thermal tuning parametersDuncan Laurie
Modify the DPTF configuration on Eve to relax the severe throttling that is currently applied and allow performance testing to see better results. BUG=b:35581264 TEST=performance tests show better results and thermal tests still pass. Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-31mb/google/eve: Add power controls to touchscreen deviceDuncan Laurie
Instead of having the SMI handler power off the touchscreen on the way into suspend add power resource controls to the ACPI device so the power is managed by the kernel instead of the BIOS. BUG=b:35581264 TEST=manual testing on Eve to ensure that the touchscreen is still functional at boot and after suspend/resume, and that it does not draw power in suspend. Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30tegra210: Remove fake cpu_reset()Julius Werner
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's pointless to pretend there is one. Most ARM SoCs/boards only define hard_reset() at the moment anyway, so let's stick with that. Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-27mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handlerPatrick Rudolph
Get rid of mainboard_io_trap_handler. The only purpose is to enable tp-smapi, but is already done on all boards in h8_enable, as of devicetree setting config0. Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-27lib/spd_bin: make SMBus SPD addresses an inputAaron Durbin
Instead of assuming the mapping of dimm number to SPD SMBus address, allow the mainboard to provide its own mapping. That way, global resources of empty SPD contents aren't wasted in order to address a dimm on a mainboard that doesn't meet the current assumption. Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-05-27google/fizz: Set GPP_C2 to NCShelley Chen
GPP_C2 is being used as strapping option, so should not be set to NF. Signal was floating previously, which can lead to an assertion of smbalert#. BUG=b:37681121, b:35775024 BRANCH=None TEST=powerd_dbus_suspend and ensure stays in suspend Change-Id: I68091206014621419b886b723a5681541be989bc Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19904 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-26mainboard/google/poppy: Add PowerResource for touchscreen deviceFurquan Shaikh
1. Do not enable touchscreen device by default in gpio configuration. 2. Select use of PowerResource for touchscreen device in devicetree so that the ACPI subsystem can take care of powering on/off the device. When system enters suspend, touchscreen device is powered off and on resume, it is powered back on. BUG=b:62028489 TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on poppy. Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19829 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-25mb/lenovo/*60: Remove not existing DIMMs from SPD mapArthur Heymans
Should result in a tiny speed bump in raminit since those addresses are not checked for present DIMMs. Checked in schematics of both Thinkpad X60 and T60 and tested to configure raminit correctly for all DIMMs populated on X60. Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-25mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447HzNico Huber
Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-25mainboard/google/eve: Update VR config settingsV Sowmya
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:38415991 BRANCH=none TEST=Build and boot eve. Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-24mb/google/soraka: Update camera sensor for sorakaNaresh G Solanki
Soraka uses OV 13858 sensor. Hence update the same. Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-24mb/google/poppy: Update SPD dataNaresh G Solanki
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD), it displays wrong part number during boot in coreboot logs. So correct part number info within the SPD. TEST= Build for Soraka & make sure part number is rightly printed. Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19692 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-24soc/marvell/bg4cd: remove cosmos mainboard and bg4cd socAaron Durbin
The SoC code was never completed. It's just a skeleton that gets in the way of refactoring other code. Likewise, the mainboard was never completed either. Just remove them both. Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19823 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-22mb/intel/wtm2: Drop unsupported native graphics initNico Huber
Since the conversion of this board to soc/broadwell in 0aa06cbf18 (wtm2: Convert to use soc/intel/broadwell), the NGI for this board is not hooked up anywhere. Also, the code doesn't compile anymore. Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-21mb/lenovo/*/romstage: Remove COM IO portPatrick Rudolph
All those boards do not have a serial port. Don't attempt to decode the COMA/COMB IO range. Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-21mb/lenvovo/*: Clean mainboard.c and devicetreePatrick Rudolph
* Move board specific SPI registers to devicetree * Remove unused headers * Remove obsolete methods * Fix coding style * Fix Thinkpad L520 SPI lvscc register Except for Thinkpad L520, no functional change has been done, just moving stuff around. Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-21mb/*/romstage: Don't lock ETR3 CF9GR in early romstagePatrick Rudolph
Do not lock ETR3 CF9GR in early romstage. As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done in bd82x6x's finalize handler. Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-21mb/gigabyte/ga-g41m-es2l: Enable IO decode range for LPT and FDDArthur Heymans
Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-20mb/gigabyte/ga-g41m-es2l: Add timestamps in romstageArthur Heymans
Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-19mainboard/google/poppy/variants/soraka: Add SPD for K3QFAFA0CM-AGCFFurquan Shaikh
BUG=b:37712455 Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19766 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 02:47:17 +0000