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Replace the AMD SMBus section with the equivalent SB800 smbus.asl
include or remove already commented-out sections.
Verified by running the cpp preprocessor over the DSDTs and diffing the
results against this patch.
The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where
someone added RADD and SADD to the OpRegion, but those are unused, so
removing them is fine.
Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10618
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Auron only has three GPIOs for RAMID, so there is no need for
sixteen SPD file entries. Only include 8 SPD entries.
Change-Id: Icf83719a2a5b9271b29f48cde5c66c4c8ccd07f4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12073
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11882
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.
Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/cpu/intel/model_6dx/acpi`, although the devices
can also use different Intel CPU models like, for example,
`intel/model_6ex` on the Lenovo T60.
Therefore move the file to the directory `src/cpu/intel/common/acpi` so
that other devices, like Intel GM45 based devices, can also include it.
Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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connections checked by desoldering the FCH and looking at the PCB
this lowers the power consumption by about 150-200mW measured on primary side
based on change #5397
Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/11866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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don't use non-volatile pointers for MMIO access
Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12081
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.
Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.
Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.
Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Merge artifact -- don't check spd_index twice.
BUG=None
TEST=Build only
BRANCH=Auron
Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234421
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
(cherry picked from commit 850125141b52886c845161434a1320676e59534d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05
Reviewed-on: http://review.coreboot.org/11912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.
In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().
BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron
Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
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Serial number is derived from the MAC address of first NIC.
Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Do this to wipe error message and hexdump of SPD from console log.
Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.
Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
internal USB EHCI controller broken, with no assigned IRQ.
PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
for the GPIO to use. They cannot be used for PCI devices at the same time.
Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9993
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11828
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Eliminate unused parameters from the console initialization.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301204
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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board_id() returns an integer which is platform-specific. 0 for one port
is different from 0 for another port. So there is no default board_id()
and hence enabling it on boards other than urara would cause build failure.
Not enabling it on urara or just setting id to "(none)" as is default results
in board_id() = 0 which means urara and an error message on console.
Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10379
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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MBa doesn't have a usable usbdebug port.
Change-Id: Ia8459daa5c9b9405c289954b28ecf1423b1f076c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Tested on T60 with intel graphics.
Change-Id: Id74d0a1315749052e7313135242e6b64862aa5e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5345
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Based on the info by Felix Held.
Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Iff1864982f2f3337c33e56976a0d4eb36f171e66
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11854
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I036c2c300b2aac38b2c30ab86623c9c46b3c5c98
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11850
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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MBA has eDP and not LVDS, so it's not supported by our native init.
Change-Id: I489b7a98163b648f0e8000202117593c6b1aaf31
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11842
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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MBA has a soldered RAM without SPD, so you need to use stored SPD.
Change-Id: I0205e6c65ccbfe7764c12c815e60801a3c3623a5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11841
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Just ran autoport on the data from MacBookAir4,2
Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11840
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.
Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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mohonpeak is the reference board for Rangeley. I doubt anyone uses it
or cares about it. We jokingly refer to it as "Moron Peak". It's code
with no known users, so we shouldn't be hauling it around for the
eventuality that someone might use it in the future.
Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11790
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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We already have two other code paths for this silicon. Maintaining the
FSP path as well doesn't make much sense. There was only one board to
use this code, and it's a reference board that I doubt anyone still
owns or uses.
Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11789
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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Remove dummy data from hwinfo.hex as it is not needed
anymore in the system.
Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11763
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Since microcode was moved to 3rdparty/blobs, we need to select
USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly.
Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11764
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Inspired by the Sage source code (itself from coreboot).
Change-Id: I4864923166efb200882d895c572d1ee060c71951
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The thermal sensor interface exposed in function 3 of the northbridge is
a more convenient and faster way to access the processor-internal
thermal sensor than using the SMBus/SB-TSI interface from the FCH, see
the Family14 BKDG: "Tctl is a processor temperature control value used
for processor thermal management. Tctl is accessible through SB-TSI and
D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the
processors cooling requirements"
Also on at least some of these boards the existing thermal zone is
broken and always returns 40C (the default value if the SMBus read
failed) because the SMBus muxing register (SmBus0Sel) is not set up
correctly.
Case in point: The fallback "smbus read failed" temperature is 40 C and
the the logs taken from the board status repository for the Asrock
E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)"
e.g.
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425
Example lm-sensors output with this patch on the pcengines APU1, on
Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and
CONFIG_SENSORS_K10TEMP enabled):
acpitz-virtual-0
Adapter: Virtual device
temp1: +54.0 C (crit = +100.0 C)
k10temp-pci-00c3
Adapter: PCI adapter
temp1: +54.0 C (high = +70.0 C)
(crit = +100.0 C, hyst = +97.0 C)
Change-Id: Id9c5b783ba424246816677099ec6651814e59f21
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add some missing devices to device tree and header.
Remove the obsolete devices.
Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The vboot verification in a stage proper is unified
replacing duplicate code in the tegra SoC code. The
original verstage.c file is renamed to reflect its
real purpose. The support for a single verstage flow
is added to the vboot2 directory proper.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11744
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=chrome-os-partner:41280
BRANCH=none
TEST=Audio jack insert/eject detection and headset buttons work
on glados with the nau8825 driver in chromeos-3.18 and the
staging kernel skl2.
Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb
Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293610
Original-Reviewed-by: Anatol Pomazau <anatol@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11720
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix the typo of _DDR to be _DDN.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build kunimitsu with iasl-20150717
Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432
Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302165
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11718
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix the typo of _DDR to be _DDN.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build glados with iasl-20150717
Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad
Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302164
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11717
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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When building for ChromeOS, it is expected that Coreboot will only occupy the
first MiB of the SPI flash, according to the veyron fmap description.
Otherwise, it makes sense to use the full ROM size.
Change-Id: I168386a5011222866654a496d8d054faff7a9406
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11117
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This is a follow-up patch to
https://chromium-review.googlesource.com/#/c/286877, after fsp support
is landed in v1.5.
BUG=chrome-os-partner:42975
BRANCH=none
TEST=execute "mosys memory spd print all" on glados and kunimitsu
Change-Id: I949e287372b190affac36a0efde8a30402eecdc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa
Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298967
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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