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2017-04-24google/fizz: Configure memoryShelley Chen
Read DRAM SPD and populate MemorySpdPtr fields in UPD data structure for FSP. BUG=b:36490168, b:35775024 BRANCH=None TEST=./util/abuild/abuild -p none -t google/fizz -x -a We are currently working on bringup and have no hardware to test on yet. Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24mb/sapphire/pureplatinumh61: Update GMA configNico Huber
This board was added while the latest libgfxinit changes were in review. Update to make it compile again and sanitize the port list. Change-Id: I81b96e225945a8f8e47b64cefea91eb2747675ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19353 Tested-by: build bot (Jenkins) Reviewed-by: Nicola Corna <nicola@corna.info>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-21mb/lenovo/t420: Enable libgfxinitNico Huber
In the single GPU configuration, the T420 has an LVDS port, one DP++ and one VGA port connected to the IGD. Docking solutions feature up to two additional DP/DVI-D ports, also directly connected to the IGD. This makes the list of ports to probe pretty long (takes about 70ms if nothing but LVDS is connected). We could save about 20~30ms if we'd limit the ports in case we are not docked or have a discrete GPU. Change-Id: I8e02c8003ff745d05ee272c59377174847f5219c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19378 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-20mainboard/google/eve: Set touchpad IRQ to level triggeredDuncan Laurie
This commit changes the interrupt configuration for the touchpad to be level triggered so it matches what the device is actually using. When the system wakes from suspend by way of touchpad interrupt, or there is touchpad input while in suspend that does not wake the device (when the device is in tablet mode) the interrupt edge is not seen by the AP so the driver does not handle the event and the touchpad keeps the interrupt asserted and does not send further interrupts. The end result is a non-functional touchpad after resume until it is reset or the driver is reloaded. This happens because the touchpad is actually treating the interrupt as level triggered and expects the kernel driver to read a data packet over I2C before it will de-assert the pending interrupt. BUG=b:35774857 BRANCH=none TEST=Test that the system can reliably wake from suspend by touchpad event via the EC and continue to have a functional touchpad after resume. Change-Id: Iaf7c04d9bc9d945bdcc196dff54c92a2a68368f3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19382 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/asus/kgpe-d16: Enable TPM when selected in KconfigTimothy Pearson
Issue TPM startup on romstage completion via common LPC TPM code if the TPM was enabled in Kconfig. Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19338 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19google/gru: change kevin boot-time center logic voltage to 925mVDouglas Anderson
Kevin's center logic isn't super clean so it needs 925 mV for center logic. All newer gru variants only need 900 mV. BRANCH=gru BUG=b:37429075 TEST=Reboot tests Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/479463 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19357 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19google/gru: change center logic voltage to 900mVDerek Basehore
It seems that we should only ever run at 900mV on center logic. Changing it to 950mV before might have just masked over problems that are now fixed. BRANCH=none BUG=chrome-os-partner:56940 TEST=on kevin, run stressapptest -M 1536 -s 1000 Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/391032 Reviewed-by: Douglas Anderson <dianders@chromium.org> Commit-Queue: Lin Huang <hl@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/19356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-19mainboard/google/poppy/variants/soraka: add soraka boardYH Lin
Create Soraka board which derives from Poppy, a KBL reference board. More Soraka specific changes need to be done later on. BRANCH=master BUG=b:36995255 TEST=Build (as initial setup) Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://review.coreboot.org/19343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19mainboard/google/poppy: Provide nhlt variant APIFurquan Shaikh
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:37375693 Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/google/poppy: Add camera supportV Sowmya
Add camera related support * Enable the SA Imaging Unit and CIO2 devices. * Enable TPS68470 PMIC and populate related ACPI objects. * Enable OV cameras and populate related ACPI objects. * Enable Dongwoon AF DAC and populate related ACPI objects. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that ACPI tables have the required entries for all the camera devices. Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18969 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19mb/google/poppy: Add Image Processing Unit ASLSowmya
This patch includes ipu.asl file in the main DSDT definition to add ACPI entries for IMGU and CIO2 devices. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: Ib7485315cb9468da7c6aa090862657a265121493 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19110 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-18mainboard/google/poppy: Clean up gpio.h fileFurquan Shaikh
1. Update formatting of gpio table to fit everything within 80 column limit. 2. PEN_RESET gpio is non-existent. Get rid of it. BUG=b:37375693 Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18mainboard/google/poppy: Enable deep S3 in DC modeFurquan Shaikh
Enable lower power state when running on battery. Deep S3 is not enabled when in AC mode to support standard "docked" config. BUG=b:36087058,b:36723679 TEST=Verified following behavior with USB mouse: 1. If AC is connected when entering S3, USB mouse is able to wake up. 2. If AC is not connected when entering S3, USB mouse does not wake up. 3. If AC is connected when entering S3 and removed after entering S3, USB mouse does not wake up. 4. If AC is not connected when entering S3 and attached after entering S3, USB mouse does not wake up. Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17mainboard/asus/kgpe-d16: Remove obsolete reference to TPM ASL fileTimothy Pearson
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static ASL file. Change-Id: I3cb2a8a3ac337d1de8a3c394d7a28155597239d0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-04-17mb/lenovo/t60: Remove PCI reset code from romstagePaul Menzel
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit bc8613ec (Fix i945 based boards) fixes that to use the correct delay of 200 ms. This code was then copied over, when adding support for the Lenovo T60. The reset was related to the shipped crypto card on the Roda RK886EX and Kontron 986LCD-M, so is not needed on the Lenovo T60. So remove it, to reduce the boot time by 200 ms. The same change is done for the Lenovo X60 in commit 7676730b (mb/lenovo/x60: Remove PCI reset code from romstage). Change-Id: Ifff43f095a1236c9e9a9ef0687e8efe42e72c971 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19298 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-15google/slippy: fix internal mic for falco/wolf variantsMatt DeVillier
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic from working properly in Windows and macOS (the Linux driver overrides the verb table, so wasn't affected). Set the verb connector/jack bits properly, to no connector / no jack detect, in order to fix. Also, make (2) small non-functional fixes: On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B both being disabled - copy/paste error). On wolf, NID 0x19 was set to an internal analog mic, where it should have been disabled (again, copy/paste error). Both these errors were introduced when consolidating/upstreaming and were not present in the original Chromium sources. Test: boot Windows [8/8.1/10] and verify mic functional with Realtek drivers on both falco and wolf. Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19262 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15mainboard/google/eve: Remove 'probed' setting from rt5663 codecDuncan Laurie
Remove the 'probed' setting from the Realtek 5663 headset codec I2C device. This was added when we had a hardware issue that was preventing I2C operation because the clock/data lines were swapped. With new and/or reworked hardware this is no longer a problem and we do not want the I2C layer in the kernel to talk to the device before the rt5663 driver. BUG=b:35585307 BRANCH=none TEST=Boot on Eve and verify rt5663 driver still loads properly. Change-Id: Ice38889e8f5d3fd1307056cab10fbe3f4e197749 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14google/slippy: clean up NGI and move to libgfxinitMatt DeVillier
- remove old, buggy NGI code from falco/peppy variants - remove superfluous INTEL_DP/INTEL_DDI configs, since already selected by northbridge/haswell - always use libgfxinit when use native init config selected - enable NGI/libgfxinit for all slippy variants The reset of the old Haswell NGI code will be cleaned up in a subsequent patchset. Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init using SeaBIOS and Tianocore payloads on peppy, wolf variants Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18824 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-14southbridge/via/vt8237r: Get rid of #include early_smbus.cLubomir Rintel
Use linker instead of '#include *.c'. The smbus_fixup() was changed not to use a structure that's defined by a northbridge since multiple different northbridges can be used. Instead the caller now directly passed the memory slot details. Change-Id: Ia369ece6365accbc531736fc463c713bbc134807 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/19082 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14mainboard/google/eve: Remove ACPI ALS deviceDuncan Laurie
Remove the ACPI ALS device from the EC configuration because this system has an ALS that is presented through the new EC sensor interface rather than the legacy ACPI interface. BUG=b:37179776 BRANCH=none TEST=Boot an Eve device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19265 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14mainboard/google/eve: Set UART0 to skip initialization in FSPDuncan Laurie
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not set back to native mode by FSP when configured as GPIO input by coreboot. Now that FSP is not touching the pins I also removed the workaround to reconfigure the pins after FSP. BUG=b:35647877 BRANCH=none TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS is booted and they are not set back to native function by FSP. Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19264 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-14mainboard/google/eve: Enable internal pull-down on USB_C{0,1}_DP_HPDDuncan Laurie
These lines act as inputs to both EC and AP and when the corresponding TCPC mux is in low power mode the line is floating. Add an internal pull-down to each GPIO to prevent it from floating in this state. BUG=b:35775012 BRANCH=none TEST=Verify that the kernel does not see a device present on DP when the TCPC mux is in low power mode. Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19263 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-13mainboard/sapphire/pureplatinumh61: Enable EuP and PMENicola Corna
With EuP and PME enabled the USB power turns off during S5. Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/19073 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-04-13mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177Venkateswarlu Vinjamuri
This configures GPIO_177 as native function. This enables OS to boot from sdcard. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13mainboard/google/snappy: Increase weida touchscreen reset delayWisley Chen
Weida touchscreen controller needs 130 ms delay after reset BUG=b:35586513 BRANCH=reef TEST=Verified that touchscreen works on power-on and suspend/resume on snappy. Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/19245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13google/eve: Disable Deep S3 in AC modeDuncan Laurie
In order to support a standard "docked" config disable Deep S3 when connected to AC power. This allows USB devices to wake the device from suspend if it is externally powered, but still retains the lower power state when running on battery. BUG=b:36723679 BRANCH=none TEST=manual testing on Eve for USB wake behavior: 1) when suspended on battery USB keyboard does not wake 2) when suspended while connected to AC a USB keyboard does wake 3) if suspended with AC, and then AC is removed, system does not wake with USB keyboard 4) if suspended without AC, and then AC is added, system does not wake with USB keyboard (it cannot get enabled without waking and re-suspending) Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19240 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13google/eve: Enable WiFi SAR featureDuncan Laurie
Enable the Intel WiFi SAR feature for Eve, which will be used to provide wifi power tables based on values read from VPD. This is enabled based on CONFIG_CHROMEOS because it relies on the presence of VPD code from vendorcode/google/chromeos. BUG=b:36727652 BRANCH=none TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables with the values that were set in VPD. Change-Id: I11c129baca891221177575108ac09ba1707b516e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19241 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13mainboard/google/poppy: Enable internal pull-down on USB_C{0,1}_DP_HPDFurquan Shaikh
These lines act as inputs to both EC and AP. Thus, add internal pull-downs to prevent them from floating. BUG=b:35648530 Change-Id: I42326c810775d5449e99e52e81870970247ce335 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19243 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13mainboard/google/poppy: Add support for cr50 SPI TPMFurquan Shaikh
Put all configs required for enabling cr50 SPI TPM on poppy under POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI TPM on this board. Also, add required callback for irq status and devicetree config for GSPI0. BUG=b:36873582 Change-Id: I67793093c006c1325fc16f669a96126525f83243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11scarlet/gru: skip display because mipi driver not readyShunqian Zheng
Scarlet don't have eDP and MIPI driver is not ready, skipping display for now or else Scarlet would be stuck in reading eDP HPD because there even not power for it. TEST=boot to kernel on Scarlet Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348 Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/19237 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-11google/eve: Limit memory SKU 5 to 1600MHzDuncan Laurie
Due to issues with stability limit the SKU with K4EBE304EB-EGCF memory to 1600MHz instead of 1866MHz. BUG=b:37172778 BRANCH=none TEST=pass stress testing on devices with this memory Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19227 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10nb/amdk8/(pre_)f.h: Don't declare global variable in headerArthur Heymans
This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-10google/eve: Update I2C bus timingDuncan Laurie
Update the I2C rise/fall timings based on newly measured values on a new board with updated pull-up resistor values. Touchscreen: rise time 98ns, fall time 38ms Touchpad: rise time 111ns, fall time 41ns TPM: rise time 112ns, fall time 34ns BUG=b:35583133 BRANCH=none TEST=Each I2C bus frequency was verified on a scope to be ~400MHz Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-07intel/minnow3: Clean up Kconfig, devicetree and FMAPBrenton Dong
This patch cleans up the code by: o adding necessary default definitions to Kconfig o removing incorrect definitions from devicetree o removing irrelevant entries from FMD file devicetree.cb and minnow3.fmd carried over a lot of code from google/reef which is not correct for Minnow3 hardware. Minnow3 is not intended to boot Chrome OS and does not need Chrome related flash regions. The erroneous code is removed. These changes are the same as those done for leafhill in commit: 6a48923 mainboard/intel/leafhill: Clean up This was tested by building with the new configuration and booting to UEFI Payload Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07mainboard/intel: Fix checkpatch errors in minnowmaxMartin Roth
This fixes the following issues, with no functional changes: ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar" ERROR:SPACING: space required after that ',' (ctx:VxV) WARNING:LONG_LINE_COMMENT: line over 80 characters WARNING:SPACE_BEFORE_TAB: please, no space before tabs ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition ERROR:SPACING: space prohibited before that close parenthesis ')' WARNING:RETURN_VOID: void function return statements are not generally useful 2 unfixed issues: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses Verified that the binary was the same before and after the changes. Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19078 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2017-04-07nb/intel/i945: Move INTEL_EDIDPatrick Rudolph
All boards select INTEL_EDID, move it to nb folder. Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19086 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-07mb/lenovo/x201: Link gpio map instead of including a headerArthur Heymans
Linking should allow to link depending on possible future variants. E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c etc. Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06amd/gardenia: Move OemPostParams() to correct fileKyösti Mälkki
The term 'callout' has a specific meaning in AGESA, meaning invoking the said function from AGESA / PI proper. OemPostParams() does not fall into that category. Change-Id: I0ad1cbf244501207af96e0ac415a5b80ced91052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-06amd/bettong: Move OemPostParams() to correct fileKyösti Mälkki
The term 'callout' has a specific meaning in AGESA, meaning invoking the said function from AGESA / PI proper. OemPostParams() does not fall into that category. Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-06gru: Initialize I2C bus for ARC2C0608Philip Chen
BUG=b:35583511 TEST=check i2c bus 0 initializes from ap console log Change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19105 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-06northbridge/via/cn700: Get rid of #include raminit.cLubomir Rintel
Using linker instead of '#include *.c'. Change-Id: Ie1bc538aa29c4f18dd6f31a83d3da58f196f2078 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/19081 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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