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2017-06-12nb/intel/gm45: Add romstage timestampsArthur Heymans
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12mb/foxconn/g41s-k: add new mainboardSamuel Holland
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O. Tested, working: * Booting Linux 4.11.3 and Windows 8.1 from USB and HDD * Resume from S3 (Linux and Windows) * Native raminit (DDR2-800) * Native graphics init (SeaBIOS, Linux) * Graphics init with VGA BIOS (SeaBIOS, Windows) * PCI-E x16 PEG slot, PCI-E x1 slot from southbridge * Realtek ALC888 HD Audio (including front panel and jack detection) * Realtek R8168 Gigabit LAN * Both SATA ports * USB 1.1 and 2.0 devices (keyboard, mass storage) * PC speaker beep * COM header * Super I/O Environment controller (temps, voltage, fans) * PS/2 keyboard and mouse * Flashing with `flashrom -p internal` * 1MiB and 2MiB SPI flash chips * CMOS gfx_uma_size Appears, OS driver loads, but otherwise untested: * IrDA header * CIR header * TPM header Untested: * S/PDIF digital audio Tested, known broken: * CMOS power_on_after_fail * USB keyboard in secondary payloads Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20027 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-12mb/emulation/spike-riscv: Update UART addressJonathan Neuschäfer
I updated my spike patch[1] to cleanly apply to current spike master. As a side effect, the UART is now at 0x02100000. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I4cb09014619e230011486fa57636abe183baa4be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/20126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-06-12soc/baytrail: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for google/rambi as to not break compilation. Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09mb/asrock/g41c-gs: Rename the board to G41C-GS R2.0 (g41c-gs_r2_0).Bill XIE
The supported "G41C-GS" with a nuvoton nct6776 superio is actually G41C-GS R2.0, which is different with the more easily-found revision G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported separately. Photos for the two revision: R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-09purism/librem13v2: Update PCI configYouness Alaoui
Update devicetree PCI config based on board spec: - enable PCIe Root Ports 5 and 9 (wifi and nvme respectively) - enable PCIe CLKREQ on RP9, disable on RP5 - enable USB OTG - enable P2SB Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1 Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Don't disable PM timerMatt DeVillier
Needed for UEFI booting via Tianocore; with PM timer disabled, payload hangs. Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Enable SATA, disable eMMC supportYouness Alaoui
Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add microcode values in KconfigYouness Alaoui
The FSP Temp RAM init will fail if the mircocode values are set to 0. A valid microcode update needs to be included and its size and offset need to be set in the config. Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19936 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add memory init codeYouness Alaoui
Adding code to setup the spd information from sodimm. Adapted from intel/kblrvp. Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09purism/librem13v2: Add GPIO pad configurationYouness Alaoui
The GPIO configuration matches the one from the original BIOS. Some configs don't make much sense, but I kept it as is so it would match (such as a NC pin with TX set to 1, or RXINV enabled). Remove unnecessary early GPIO config. Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19934 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Select SERIRQ_CONTINUOUS_MODEMatt DeVillier
Like other devices using ENE embedded controllers, the librem13v2 requires this config option for the PS2 keyboard and mouse (trackpad) to function properly. Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v2: Add initial directory for librem13 v2Youness Alaoui
Add the initial directory for the port of the Librem 13 v2. The base implementation was copied from the google/chell directory and the chell references were replaced. spd directory was removed since the RAM is not soldered on the MB. The Kconfig, board_info.txt and devicetree.cb files were modified to match the Librem 13 v2 hardware information. The romstage.c, mainboard.c, Makefile.in and dsdt.asl were modified to remove chromeos specific code. The boardid.c, chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c files were removed from the tree, and the acpi directory was replaced with the acpi directory from the purism/librem13 board. These changes allow us to remove the references to chromeos specific code and allow coreboot to compile when the librem13v2 board is selected. Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09purism/librem13v1: Set FADT revision to ACPI 3.0Matt DeVillier
The FADT revision was set to 5, but we do not implement the ACPI v5.0 specification, which prevents Windows from booting. Setting it to v3 (matching most other boards) fixes the issue and Windows now boots normally. Bug found by Matt DeVillier, fix tested by Youness Alaoui on Librem 13 v1 hardware. Please also see commits 00d250e2289de (intel/skylake: Switch FADT to ACPI version 3.0) [1] and 27e6042bb7d0b1 (intel/apollolake: Switch FADT to ACPI version 3.0) [2]. [1] https://review.coreboot.org/19453 [2] https://review.coreboot.org/19146 Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09purism/librem13v1: Rename librem13 to librem13v1Youness Alaoui
A simple rename of the directory and the config values and string in Kconfig/Kconfig.name/board_info.txt It will be less confusing for users since the first models are referred to as 'v1' everywhere now. Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19931 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-09soc/braswell: fix scope for I2C ACPI devicesMatt DeVillier
For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for intel/strago and google/cyan as to not break compilation. Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09google/chell: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-09cpu/intel/model_206ax: Use tsc monotonic timerPatrick Rudolph
Switch from lapic to tsc. Allows timestamps to be used in coreboot, as there's a reference clock available to calculate correct time units. Clean Kconfig, remove duplicated lapic code and include tsc dir for LGA1155 boards. Tested on Lenovo T430. Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09mb/google/soraka: Update UF camera i2c addressNaresh G Solanki
Update user facing camera i2c address to 0x36. BUG=None TEST=Build & boot on soraka. Make sure user facing camera is detected. Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
Provide all gfx init methods as a Kconfig `choice`. This elimates the option to select native gfx init along with running a Video BIOS. It's been only theoretically useful in one corner case: Hybrid graphics where only one controller is supported by native gfx init. Though I suppose in that case it's fair to assume that one would use SeaBIOS to run the VBIOS. For the case that we want the payload to initialize graphics or no pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the choice. If multiple options are available, the default is chosen as follows: * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS, * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS, * NATIVE_VGA_INIT, if we don't add a Video BIOS. As a side effect, libgfxinit is now an independent choice. Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07mainboard/google/poppy: Add support for ELAN deviceFurquan Shaikh
Add support for ELAN 5515 device. BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07via/epia-m700: Wrap long line in commentPaul Menzel
Wrapping the long line tries to address a warning by `checkpatch.pl`, but the line is still over 80 characters long. Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20033 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-06asus/kgpe-d16: Add video card ID for VGA BIOS namePaul Menzel
The comma-separated PCI vendor and device ID is used to associate the VGA BIOS to the video device by using it as the file name of the VGA Option ROM. Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06mb/*/*/cmos.layout: Make multibyte options byte alignedArthur Heymans
Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-05google/reef: Add coralPatrick Georgi
A new variant copied from reef. Allow override of the SKU. Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20020 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-04google/rambi: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each rambi variant has a different USB port config. Port data currently available for only candy and squawks; other variants to be added once data obtained. Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/jecht: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each jecht variant has a different USB port config. Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/auron: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each auron variant has a different USB port config. Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/slippy: populate PEI SPD data for all channelsMatt DeVillier
Since dual-channel setups use same RAM/SPD for both channels, populate spd_data[1] with same SPD data as spd_data[0], allowing info for both channels to propogate into the SBMIOS tables. Clean up calculations using SPD length to avoid repetition. Changes modeled after google/auron variants. Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-04google/parrot: make chromeos.c compilation conditional on CONFIG_CHROMEOSMatt DeVillier
No reason to compile/include chromeos.c for non-ChromeOS builds Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04google/lulu: enable SATA device to sleep in S0Matt DeVillier
sata_devslp_disable was set to work around some buggy SSD firmware, but as it's disabled by default in both Linux and Windows, no reason to disable at the firmware level when many properly-functioning SSDs can take advantage of power savings. Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-04mb/google/poppy: Update camera sensorNaresh G Solanki
Update camera sensor detail to OV 13858 Also update i2c address of OV5670 BUG=None TEST= Build & boot to ChromeOS. Check for both the camera detection. Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-03mb/lenovo/*/cmos: Remove unused option and checksum fixPatrick Rudolph
Fix for all Sandy-Bridge and Ivy-Bridge devices. Remove unused option "hyper_threading". Increase CMOS checksum range to cover all user adjustable settings. Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-03mb/google/fizz: set SD_CDZ to edge trigger.Kane Chen
This is to align with the SD_CD GpioInt setting in acpi BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/20001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER. * Let drivers select it if they are in charge. * Don't select it on the mainboard level if a driver handles it. Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02intel/bakersport_fsp: Move into bayleybay_fsp as a variantMartin Roth
The separate directory was the old way of handling variant boards. Update bakersport_fsp to the new method. All of the other pieces were already moved into bayleybay_fsp. Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/19077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-02google/rambi: disable PCI device for unused i2c busesMatt DeVillier
Light sensor isn't used and ACPI already removed, so disable I2C5 bus interface as well. Disable I2C6 for devices without a touchscreen Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-02mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selectionAamir Bohra
Remove MONOTONIC_TIMER_MSR selection from mainboard Konfigs, as it only does a reduntant selection of HAVE_MONOTONIC_TIMER config, already selected under skylake soc Kconfig. Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20002 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02mb/intel/d410pt: Add mainboardArthur Heymans
This board is almost identical to D510MO, the only differences are some differences in populated connections, CPU with less L2 cache and a 10/100 Realtek NIC. The vendor uses the very same binary for both D510M0 and D410PT. Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-01mainboard/google/poppy: Enable H1 I2C TPMFurquan Shaikh
Enable H1 I2C TPM in Kconfig and devicetree for poppy. CQ-DEPEND=CL:513513,CL:*381534 BUG=b:36265511 BRANCH=None TEST=Compiles successfully. Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31mainboard/google/poppy: Power down camera rails when suspendingFurquan Shaikh
BUG=b:62147763 Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31google/slippy: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each slippy variant has slightly different USB port config; data for falco and leon to be added once available Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31google/beltino: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. All beltino variants use the exact same USB port layout. Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31google/parrot: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Move inclusion of mainboard.asl after southbridge asl files so scopes referenced in usb.asl are valid. Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31mb/lenovo/t430: Fix PCIe hot-plug portsPatrick Rudolph
Port 0 is connected to SD-card reader. Don't mark it as hot-plugable. Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:49:07 +0000