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2009-04-30Refactor copy_and_run so that it uses a single code base instead ofPatrick Georgi
3 (with one of them way too much assembler code). On the way, I had to make some changes to the way the code is built, which is an effort I want to expand over time. Right now, large portions of the in-ROM part of coreboot is compiled as a single file, with lots of .c files including other .c files. That has its justification for pre-raminit code, but it also affects lots of post-raminit code (memcpy doesn't really make sense before raminit, or at least CAR) The coreboot_apc code (AMD boards) gained some .c includes because I don't know that part of the code enough to really rework it and only have limited possibilities to test it. The includes should give an identical situation for this part of the code. This change was posted as set of 6 patches to the list, but they were mostly split for review purposes, hence commit them all at once. They can still be backed up using the patch files, if necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28Enable HAVE_HIGH_TABLES by default for northbridges withPatrick Georgi
support for it. The related mainboards don't need to activate it themselves anymore. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28add_mainboard_resources is necessary for some boards (eg. kontron), butPatrick Georgi
this generic code could be added to the caller of add_mainboard_resources (wrapped in HAVE_HIGH_TABLES, of course). That way, boards that really need it (for other things) can use this function, while others don't have to do anything to use HAVE_HIGH_TABLES. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27Add high table support to via vt8454c.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27Add high tables support for Supermicro H8DME.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27Migrate via/vt8454c to CBFS.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25Enable CBFS for qemu and kontron. Both are builds-and-runsPatrick Georgi
tested, incl. optionrom-in-cbfs for kontron, and compressed payloads for both. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22Convert 12 more boards to use include statements in Config.lb.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22Trivial patch. I forgot to update K8_SET_FIDVID.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22This patch adds the target hp/dl145_g3 together withMondrian nuessle
the appropriate mainboard sources. Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de> Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com> I updated some whitespace and the Config files. - Myles git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22drop duplicate compiler options that are already mentioned in CFLAGS.Stefan Reinauer
(scan-build chokes on this) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22no duplicate names in cmos.layout allowed. (fixes a bunch of boards)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to aStefan Reinauer
combined socket_mPGA604. No other sockets come with clock rates, and there is no difference in code, except for the number of microcode patches included in a build. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21CONFIG_CHIP_NAME is dead (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21Thanks to Myles' patch adding support for include statements,Carl-Daniel Hailfinger
refactoring Config.lb became possible. Factor out ROM size calculation from Config.lb. This patch converts 87 boards (with and without USE_FAILOVER_IMAGE), but it has to work around a parser bug. 89 files changed, 209 insertions(+), 2415 deletions(-) A total of 2206 removed lines. Abuild works for all changed boards on khepri. Myles writes: I've tested serengeti for the failover portion and s2892 for the nofailover portion. ldoptions are exactly the same and they both boot the same. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20Fix implicit declarations of done_cache_as_ram_main by adding aCarl-Daniel Hailfinger
prototype for these assembler functions. Affected boards: digitallogic/msm800sev pcengines/alix1c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18Add support for the ASUS P2B-D mainboard.Uwe Hermann
This is a pretty standard "yet another 440BX" target, so the code is pretty straight-forward. It's a dual-CPU machine, which might need some fixing, I'm booting with 'maxcpus=0' for now. It does boot successfully up to a Linux login prompt, though. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17Add VIA CX700 support, plus VIA vt8454c reference board support.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-16I deleted mptable.c in my patch, but forgot to svn rm it.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15This patch cleans up mpspec.h and allows it to be included whenMyles Watson
HAVE_MP_TABLE=0 It also removes the artifacts from the Asus m2v-mx_se that were necessary before the change. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15r4097 broke the tree and it remains unfixed :-( Stefan Reinauer
Repeat: Cosmetic patches shall not break the tree for 20 revisions. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14EPIA-CN does not have any ACPI tables. Fixes manual and auto build here.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13I need to do uses HAVE_ACPI_RESUME for each board. Here we go.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> It should fix the build break introduced in r4101 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Following patch adds support for the ACPI resume on Asus M2V-MX SE. The ACPIRudolf Marek
code just blinks the leds. The motherboard resources are use to reserve coreboot used memory. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Fix the following errors:Carl-Daniel Hailfinger
In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93: src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of function ‘activate_spd_rom’ In file included from src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101: src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’: src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of function ‘soft_reset’ In file included from src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98: src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’: src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of function ‘activate_spd_rom’ Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-12This patch cleans up the calls to $CC in mainboard Config.lb files. TheyCarl-Daniel Hailfinger
now all have the same parameter order. action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -o $@" The idea behind this parameter order is: - *FLAGS at the beginning. - Use a common set of *FLAGS. - Include files and directories listed afterwards. - nostdinc, nostdlib, no-builtin tell the compiler this is standalone code. - Warnings. They do not influence source or compilation. - Compilation strategy (small) and output mode (asm or binary). - File to be compiled. - Output name. - $(DEBUG_CFLAGS) and -S are only used for asm output. Other changes in this patch: - src/supermicro/h8dme/Config.lb now uses $DEBUG_CFLAGS instead of hardcoding the respective flags. - $DEBUG_CFLAGS was added to asm outputting $CC calls: supermicro/h8dme/Config.lb lippert/roadrunner-lx/Config.lb - $DISTRO_CFLAGS was added to some $CC calls in: iwill/dk8_htx/Config.lb (CAR AP code) supermicro/h8dmr/Config.lb (CAR AP code) supermicro/h8dme/Config.lb (CAR AP code) gigabyte/m57sli/Config.lb (CAR AP code) gigabyte/ga_2761gxdk/Config.lb (CAR AP code) amd/serengeti_cheetah_fam10/Config.lb (everywhere) msi/ms7135/Config.lb (everywhere) nvidia/l1_2pvv/Config.lb (CAR AP code) -$CFLAGS was added to all $CC calls in: amd/db800/Config.lb amd/dbm690t/Config.lb amd/norwich/Config.lb amd/pistachio/Config.lb amd/serengeti_cheetah/Config.lb amd/serengeti_cheetah_fam10/Config.lb arima/hdama/Config.lb artecgroup/dbe61/Config.lb asus/a8n_e/Config.lb asus/a8v-e_se/Config.lb asus/m2v-mx_se/Config.lb broadcom/blast/Config.lb digitallogic/msm800sev/Config.lb gigabyte/ga_2761gxdk/Config.lb gigabyte/m57sli/Config.lb ibm/e325/Config.lb ibm/e326/Config.lb iei/pcisa-lx-800-r10/Config.lb iwill/dk8_htx/Config.lb iwill/dk8s2/Config.lb iwill/dk8x/Config.lb kontron/986lcd-m/Config.lb lippert/roadrunner-lx/Config.lb lippert/spacerunner-lx/Config.lb msi/ms7135/Config.lb msi/ms7260/Config.lb msi/ms9185/Config.lb msi/ms9282/Config.lb newisys/khepri/Config.lb nvidia/l1_2pvv/Config.lb pcengines/alix1c/Config.lb sunw/ultra40/Config.lb supermicro/h8dme/Config.lb supermicro/h8dmr/Config.lb technexion/tim8690/Config.lb tyan/s2735/Config.lb tyan/s2850/Config.lb tyan/s2875/Config.lb tyan/s2880/Config.lb tyan/s2881/Config.lb tyan/s2882/Config.lb tyan/s2885/Config.lb tyan/s2891/Config.lb tyan/s2892/Config.lb tyan/s2895/Config.lb tyan/s2912/Config.lb tyan/s2912_fam10/Config.lb tyan/s4880/Config.lb tyan/s4882/Config.lb - Use $@ wherever appropriate. - Kill that evil CACHE_AS_RAM_AUTO_C variable. - Trailing whitespace fixups on lines which were touched anyway. We now only have 6 remaining different calls to $CC whereas before there were 20. If I am allowed to rename src/mainboard/kontron/986lcd-m/auto.c to src/mainboard/kontron/986lcd-m/cache_as_ram_auto.c, we're down to 4 different calls. If we can decide on the use of $CPU_OPT, we are down to 3 different calls. One additional point I'd like to clear up: if ASSEMBLER_DEBUG makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm end "-dA -fverbose-asm" is only useful for asm output. For these flags, DEBUG_CFLAGS is a total misnomer. What about calling them DEBUG_ASMCFLAGS or somesuch? "-g" should be controllable by a separate switch. It is useful even for object code. The following targets are broken by this patch because they contain implicit declarations, but the error did not trigger due to missing CFLAGS: amd/serengeti_cheetah asus/a8v-e_se asus/m2v-mx_se digitallogic/msm800sev pcengines/alix1c supermicro/h8dme supermicro/h8dmr Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11Bring S2912 and S2912_Fam10 Config.lb in line with each other.Carl-Daniel Hailfinger
- Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c - Compile apc_auto.c with $(DISTRO_CFLAGS) - Clean up whitespace If anyone can explain the remaining differences in Config.lb which are NOT caused by the K8/Fam10 switch, I'd be glad to hear them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11Kill remaining unneeded CAR/ROMCC if-blocks.Carl-Daniel Hailfinger
Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although USE_DCACHE_RAM is always set for them. Such checks are not only pointless, they actively make the files hard to read. A full abuild run confirmed that compilation did not change with this patch applied. The patch does not change whitespace of the remaining code to ease review and svn blame. With this change, it should be possible to have two or three Config.lb variants in total (except the actual hardware config). Right now, some Config.lb have comments, some don't, some have empty lines for better readability, some don't, some have leading whitespace, some don't. This is an utter mess and unifying these files would certainly reduce the headaches I have when looking at them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-08fix sandpointx3_altimus_mpc7410 target. We're back at all boards compiling.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-07This tested ok, but qemu can't really handle c0000 as RAM.Ronald G. Minnich
(trivial) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-07This is a bit of an emergency fix for qemu. Ethernet routing has not been Ronald G. Minnich rminnich
working. Given all the limitations of PIRQ routing we keep it simple and just set the IRQ directly. Most BIOSes are doing setup this way anyways, since there are so many errors in PIRQ tables. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06Some changes for option roms: Ronald G. Minnich
- don't make users pick the name. Names for option roms are in the v3-defined format of pci%04x,%04x.rom with the vendor and device id filling in the %04x. - users pass in vendor and device id. - users pass in a dest. If the dest is 0, the address of the ROM image in FLASH is returned. If the address is non-zero, then the decmpressor is called, and it will make sure the ROM image is copied to the destination (even in the uncompressed case). move qemu over to always using ROMFS Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06Daniel Toussaint wrote:Daniel Toussaint
As I mentioned a few weeks ago, I am in the process of porting this board: http://www.technexion.com/products/embedded_boards/tim-8690-mt.html This board has a dual BIOS , choosable with a jumper - much like the BIOS savier from before - so it is a pleasure to work with as a linuxbios developer. It is still a work in progress, however , I already submit the patch. All on board devices and slots work as expected, only need some more stress testing with the RAM, acpi, etc.. Signed-off-by: Daniel Toussaint <daniel@dmhome.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05cross compilation fix for motorola sandpoint based boardsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05two more totalimpact briq fixes. Gets us back to the romfs breakage on PPCStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04fix configuration step of totalimpact briq and embeddedplanet ep405pc.Stefan Reinauer
(trivial). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Fix up the incomplete commit in r4055.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03There are more than a dozen targets in the v2 tree which refer to ROMCCCarl-Daniel Hailfinger
in their Config.lb but never use it. There's no point in keeping dead code around. This patch removes ROMCC remainders from Config.lb and kills orphaned auto.c and failover.c in the affected mainboard directories. arima/hdama ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x msi/ms9282 newisys/khepri sunw/ultra40 tyan/s2891 tyan/s2892 tyan/s2895 tyan/s4880 tyan/s4882 Abuild log is completely identical with and without the patch. With this patch, the last ROMCC remainders for K8 boards are gone. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Next step. Kill auto.c and failover.c and clean up Config.lb forCarl-Daniel Hailfinger
tyan/s2735 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s2885 tyan/s2891 tyan/s2892 tyan/s2895 Abuild log is completely identical with and without the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03There are more than a dozen targets in the v2 tree which refer to ROMCCCarl-Daniel Hailfinger
in their Config.lb but never use it. There's no point in keeping dead code around. Kill it. This patch removes ROMCC remainders from Config.lb for tyan/s2735 and tyan/s2850. Abuild build log with and without the patch is completely identical. More patches of the same type can be done, hopefully making ROMCC dependencies a bit more clear for v2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Forgot CONFIG_ROMFS for supermicro/h8dme.Patrick Georgi
Trivial fix, just add the defaults as with all other boards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31Add the CONFIG_ROMS config variable. Ronald G. Minnich
Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31cosmetic fix for function definition.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21To make use of HAVE_HIGH_TABLES following patch is needed. Also, it movesRudolf Marek
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21To make use of HAVE_HIGH_TABLES following patch is needed. Also, it movesRudolf Marek
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20Add Supermicro h8dm3 mainboard. This is mostly a copy from the h8dmr.Marc Jones
The one issues is the SPD address switch for the second CPU. That means that the memory must be an exact match on each CPU. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17- TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in theCarl-Daniel Hailfinger
DSDT and use the dynamic TOM2 variable instead. - The DSDT needs to be revision 2 or above to handle 64 bit variables. This will require a recent (not older than 2007) iasl (ACPI compiler). - Fix an incorrect comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15Fix all build problems on PPC except the _SDA_BASE issues caused by theStefan Reinauer
code expecting too old binutils(?). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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