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BUG=b:173709409
BRANCH=dedede
TEST=EE measured result is 390.8kHZ
Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop
delay time from 100 ms to 160 ms.
The power sequence is not met with the latest guide_rev.0.6.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the measured waveform complies with Goodix touchscreen spec.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Broadwell boards use 8 for MAX_CPUS, so this option can be factored
out into SoC Kconfig.
Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it
from every mainboard where 8 is used.
Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Haswell and Broadwell have at most 8 threads.
Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46952
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Voema port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
BUG=b:176462544
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=Verify PCI IRQ: log messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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They aren't specific to AC power operation anymore. Also adapt autoport.
Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All mainboards use the same values for AC and battery, even desktop
boards without a battery. Use the AC values everywhere and drop the
battery values. Subsequent commits will rename the AC power options
accordingly, and will also clean up the corresponding acpigen code.
This is intentional so as to ease reviewing the devicetree changes.
Also update util/autoport accordingly.
Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C
connections enter DP alt mode, which should wake the system from S3.
Configure S3 wake events to include MKBP so this actually wakes
the system.
BUG=b:174121852
BRANCH=zork
TEST=Generating DP event on MKBP via EC console wakes morphius
Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019
TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable IPU for voema for MIPI camera.
BUG=b:169551066
TEST=IPU is enabled and shows in lspci.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49002
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built kontron/boxer26 with BUILD_TIMELESS=1, coreboot.rom remains the
same.
Change-Id: I08bd68aa2f98f93b8c5daf1ab2f3c1bbce521c53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ibc6833d9256800d0e50651cac18a4e81ddbe6895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48144
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move include directories from carriers and variants to mainboard level
being able to reuse them later. Also, rename guards so that they fit
their usage.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48142
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix off-by-1 count of NID entries.
Change-Id: I65f70d084022c99233144b460542a793eae2acf3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH.
PUFF-based variants do not have an internal panel, so do not need this.
Test: build/boot Windows 10 20H2 on google/akemi, verify
display backlight controls functional.
Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables backlight control under Windows 10.
Test: build/boot Windows 10 20H2 on google/reef, verify
display backlight controls functional.
Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Converts bit field macros to target PAD_CFG_*() macros. To do this,
the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/
gpio.h
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Add functions to read the system and mainboard serial numbers
from VPD tables stored in flash.
Remove board-specific implementations for google/drallion and
google/sarien and select the new Kconfig instead.
Test: build/boot google/akemi with RO_VPD region persisted from
stock Google firmware, verify system/mainboard serial numbers
present via dmidecode.
Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove index0 DRAM assignment since it doesn't use in any build.
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id
BUG=b:175911098
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I853a316c266afafeecff67b263005a77be316e2b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PUFF-based Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible
regardless of display init type used.
Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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These Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot one of each variant, ensure boot splash/menu
prompt visible regardless of display init type used.
Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
[2] https://review.coreboot.org/c/coreboot/+/47417/2/src/mainboard/google/hatch/variants/baseboard/gpio.c#b182
Tested successfully on Clevo L141CU.
Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Enables backlight control under Windows 10.
Test: build/boot Windows 10 20H2 on google/ampton, verify
display backlight controls functional.
Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48751
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the panel settings dumped from vendor firmware and hook up
drivers/intel/gma, which will be required for brightness control.
Keyboard brightness control still requires ACPI code. This will be done
in a separate change later.
Test: Panel gets enabled when the payload starts on Clevo L141CU.
Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.
Formula for conversion of power cycle delay:
gpu_panel_power_cycle_delay_ms =
(gpu_panel_power_cycle_delay - 1) * 100
Formula for all others:
gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10
The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.
Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Some bridge chip or panel requires dsi signal output before dsi
receiver works.
BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.
Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.
Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.
Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver and set the pad's initial value to 0 since the signal is active-
high and shall be set by the IPMI/BMC driver.
Also add the pad to early gpio config, since it is expected to have an
external pull-up like X11SSM-F, which is wrong and would confuse the BMC.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver.
Also add the pad to early gpio config, since it has an external pull-up,
which is wrong and would confuse the BMC. Set the pad's initial value to
zero since the "POST complete" signal is active-high and shall be set by
the IPMI/BMC driver.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value.
Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.
Tested successfully.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8581556d915cbad2c743a79db273479ba55798fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88.
Reason for revert: Build bot fails.
Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On commit 64c03e3c ("mb/google/poppy: Fix race condition in acpi"),
we introduced a new Power Resource common to all the camera modules,
in order to resolve a race condition when both modules were in use
(e.g. during startup).
The nautilus variant also used the Power Supply I2C2.PMIC.OVTH, which
requires the new common PR, but the new dependency was not added.
Depend on the new Camera Common Power Resource.
Fixes: 64c03e3c ("mb/google/poppy: Fix race condition in acpi")
BRANCH=poppy
BUG=b:174941580
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: Ifa6c70b7c02aec0112189eca573e76e53175d70d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
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Initiate peripheral buses based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We don't know exactly for what the GMM PCI device is used for or how it
is used. Thus, remove it to fallback to default-disable.
Change-Id: I4b8b33b16527cbcc21168b995cbfdb54a2fa3cac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.
Change-Id: I7c537bba75d66badf854f9e7b6799303a7af018e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.
Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is required for CbNT.
Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add SMBIOS slot descriptions for M.2 ports and remove duplicate
comments.
Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update galtic device tree override to match schematics.
BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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