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2021-05-20mb/asus/h61-series: Consolidate devicetree SATA optionsAngel Pons
The H61 PCH only supports 4 SATA ports, and does not support Gen3. Change-Id: I3e060ca6904fd6c773c322988a17bbca28333a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/h61-series: Relicense devicetrees as GPL-2.0-or-laterAngel Pons
I added these devicetrees in commit 65ddbb720b1 (mb/asus/p8h61-m_pro: Add new mainboard) and commit fe7c2b996bbb (mb/asus/p8h61-m_lx3_r2_0: Add new mainboard). To ease licensing matters when transforming these boards to use overridetrees, relicense the devicetrees so that all of them use the GPL-2.0-or-later license. Change-Id: Id26d0d9dd6cbb81d6a6a263feab7f36ddb4ff6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hexAngel Pons
Done for consistency with the other variants. Tested with BUILD_TIMELESS=1, Asus P8H61-M LX remains identical. Change-Id: I440706f6fa11d3c2410c445cb7e946c063578c4e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-20mb/asus/p8h61-m_lx: Transform into variant setupAngel Pons
Handle some differences in the DSDT code using preprocessor. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I2a02f32dfd9fa9c1adce3baf0d279ea19db5883f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-20mb/ocp/deltalake: Implement skipping TXT lockdown via VPDArthur Heymans
This allows to skip TXT Lockdown via "skip_intel_txt_lockdown" VPD parameter. Change-Id: Ic5daf96bdda9c36054c410b07b08bcd3482d777c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rocky Phagura Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-20mb/google/mancomb: Enable GFX HDA deviceIvy Jian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in mancomb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I47cf9a9dc73fd47e390b079bb9eaa14dc364404a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/google/guybrush: Add SoC thermal zoneRaul E Rangel
The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/asus/f2a85-m_pro: Set resources for 2e.bPaul Menzel
The v4 resource allocator logs the error below: […] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed) update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: f000, Tag: 100 PCI: 00:01.0 14 * [0x1000 - 0x10ff] limit: 10ff io PCI: 00:11.0 20 * [0x1100 - 0x110f] limit: 110f io PCI: 00:11.0 10 * [0x1110 - 0x1117] limit: 1117 io PCI: 00:11.0 18 * [0x1118 - 0x111f] limit: 111f io PCI: 00:11.0 14 * [0x1120 - 0x1123] limit: 1123 io PCI: 00:11.0 1c * [0x1124 - 0x1127] limit: 1127 io ERROR: Resource didn't fit!!! PNP: 002e.b 62 * size: 0x2 limit: fff io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done […] === Resource allocator: DOMAIN: 0000 - resource allocation complete === […] PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io PNP: 002e.b e2 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq PNP: 002e.b e4 <- [0x00000000f1 - 0x00000000f0] size 0x00000000 gran 0x00 irq ERROR: PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree […] So configure it, to use the resources from port 0. TEST=With CB:54669 boot Asus F2A85-M PRO to SeaBIOS/GRUB and Debian’s Linux 5.10.28 Solution-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: Ibfedca96e4b5ad17f99bc84e2fbf7d0a6aad4484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54670 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/kukui: Add rt1015 support for katsuSunway
Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb BUG=None BRANCH=kukui TEST=Speaker can work normally in katsu during firmware stage Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/sarien/var/sarien/hda_verb: Indent unindented commentsPaul Menzel
Change-Id: I2d08fa7506c6230491273f57ee0116927b29abe3 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/drallion/var/drallion/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). The file was an exact copy of `src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h` added in commit 95370e1f (mb/google/sarien: Add HD Audio verb table). Change-Id: I43cd73a14e07eb4518e3d44b6f81dff5016da721 Fixes: e3443d87 ("mb/google/drallion: Add new mainboard") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/sarien/var/arcada/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). Change-Id: Id8a099297bd8bcebf9734e1beee2449fdcca75c5 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/mancomb: Enable AMD I2S Machine DriverIvy Jian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. Also configure Audio Co-processor(ACP) to operate in I2S TDM mode. BUG=b:187860242 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I528f90d81a418236e512a1e0840ff44c3a3a983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20baytrail: Factor out INT15 handlerAngel Pons
The handler is the same on all Bay Trail mainboards. Factor it out. Change-Id: Ia1b6faaca4792cda5f14948d23498182bf4bb2c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54415 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/dedede: move discrete TPM in overridetree for lalalaAaron Durbin
Move discrete TPM in the devicetree to avoid emitting the following message: "Using default TPM ACPI path: '\_SB_.PCI0.LPCB'" There is no corresonding ACPI device for 1f.5 PCI device. Therefore, move the discrete TPM to a device that has the corresponding ACPI device node. Functionality should remain the same. BUG=b:187518267 Change-Id: Ie9ec70336d5651c87f06f8b357abd1bfdb1cc06b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-05-19herobrine: Enable macronix SPI configShaik Sajida Bhanu
Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19mb/google/brya/brya0: Manually probe fw_config for DB_LTETim Wawrzynczak
In order to use the USB WWAN module in USB mode (as opposed to PCIe), the PCIe RP must be turned off at the FSP level. The `probe` statement in the devicetree unfortunately takes effect too late, because the UPDs for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas fw_config probing for devicetree is done in ramstage. Add a new variant-specific file which will handle manually setting the UPD based on FW_CONFIG instead. BUG=b:180166408 TEST=set CBI FW_CONFIG field to LTE_USB, see message in console, set field to LTE_PCIE, do not see message in console. Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number, PLD and power_gpio for each DFP. BUG=b:186521258 TEST=Validated Retimer firmware upgrade along with upstream kernel under no device attached scenario. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I18f29ce5f8450a8b0f8208a60b8b607f9f0d8817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52714 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52711 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Disable dynamic GPIO PM for community 3Maulik V Vaghela
We recently added GPIO definition for PCIE vGPIO for Alder Lake. We also need to disable GPIO dynamic PM for this community which is already done for other communities as well. BUG=b:188392183 BRANCH=None TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also disabled Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/h61m-cs: Transform into variant setupAngel Pons
To preserve reproducibility, temporarily guard mainboard.c contents. This will be removed once all boards have become variants. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I1ffb41470d24713a4a7f0689958b733d4b1bdf52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_pro: Transform into variant setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_lx3_r2_0: Transform into variant setupAngel Pons
Get ready to squash all Asus H61 boards together, so as to factor out lots of redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I738197bf4d5ea8b879ae26ecbcb0cf3714316662 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/{h61m-cs,p8h61-m_lx}: Reorder `_PTS` and `_WAK`Angel Pons
Done to preserve reproducibility when switching to a variant setup. Change-Id: I78241c807f767846774b8e1a2e0d25f3452ed544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18Asus H61 boards: Align dsdt.asl with other boardsAngel Pons
Prepare to transform Asus H61 boards into a variant setup. Change-Id: Ifd5808edac22ebdba9b29a711ad129b91d9975d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18mb/asus/h61m-cs/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: I91ee7dc601f1fc52a7d68f66555143156b91ebf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54365 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_lx/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: Ia5a8d36f78db2262b4c8d48cbb4dd16718d01475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54364 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_pro/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: I96486d57250e901d872e4ef12967c2aadd9791ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54363 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_pro: Relicense gma-mainboard.adsAngel Pons
Commit 65ddbb720b1 (mb/asus/p8h61-m_pro: Add new mainboard) added this file, and I authored this commit. Since most gma-mainboard.ads files are licensed as GPL-2.0-or-later, relicense this one for consistency. Change-Id: I2d28150f4c97ba600cb46fead7bb29cdc65c5baf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54362 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18LGA1155 boards: Drop `VGA_BIOS_{FILE,ID}` for iGPUAngel Pons
These boards have a socketed CPU, and the PCI device ID for the iGPU depends on the installed CPU. Specifying a default doesn't make sense. Change-Id: Iee6749e4fb691f09664cc6ffb3cbf66e4230fa9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54361 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mainboard: Use decimal for `device lapic 0x0 on`Angel Pons
Most boards use `device lapic 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18mainboard: Use decimal for `device domain 0x0 on`Angel Pons
Most boards use `device domain 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18mainboard: Use decimal for `device cpu_cluster 0x0 on`Angel Pons
Most boards use `device cpu_cluster 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18mb/google/dedede: To support ELAN Touchpad device on I2C0Alex1 Kao
Add ELAN Touchpad device under I2C0 BUG=b:188373661 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52936 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIGDtrain Hsu
Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-18mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ecMaulik V Vaghela
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps rebooting with hash error. Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-18mainboard: Drop useless `acpi_tables.c` filesAngel Pons
The `tcrt` and `tpsv` values in GNVS can be used to implement thermal management in ACPI. However, not all mainboards use these values. On mainboards where `tcrt` and `tpsv` are not used in ACPI tables and are the only values set in the `mainboard_fill_gnvs` function, remove them as well as the entire `acpi_tables.c` file. Most files come from autoport, which unconditionally generates this file. Change-Id: If2315ddd9700e2da0a24ffecc20acb5c1a1d688e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-18mb/ocp/deltalake: Rearrange slot table for remapping type 9 Slot IDJohnny Lin
Change-Id: I07bdf7f85f8411e04da8a94da7de1e7b93c9e921 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-05-18mb/google/cherry: Pass reset gpio parameter to BL31Yidi Lin
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-16mb/google/mancomb: enable DDI0-DP portIvy Jian
Configure DDI-0 connector type to DP. BUG=b:187856682 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-14mb/google/volteer: Configure TCSS OC pinsNick Vaccaro
TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/cherry: Add DRAM calibration supportRex-BC Chen
Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-05-14mb/google/dedede/var/boten: Modify DPTF parametersStanley Wu
DPTF parameters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/google/zork: update DRAM table for berknip/dirinboz/gumbozKevin Chiu
Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-14mb/amd/majolica: Disable IO ports 0x60/0x64Raul E Rangel
I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-14mb/clevo/n130wu: Use device alias names in devicetreeFelix Singer
Switch to device alias names in devicetree. Remove unnecessary comments since the names are self-explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-26 21:47:44 +0000