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2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct PCIe port setupAngel Pons
Coalescing is not needed, as all PCIe ports are used. Change-Id: Icf31f6672e0a54d119a6537da1b52c42f9cee823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39740 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61m-*/devicetree.cb: Add missing IRQAngel Pons
IRQ 0x70 was not declared for device 2e.7, and coreboot whined about it. Change-Id: If40aa390722cf253169003129b31f20543fde5dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39739 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct subsystem IDAngel Pons
Linux does not handle either value in any special way, though. Change-Id: I833cb94e65b9ddfb79edbcdd0216c70740aa4a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23src/mb/google/volteer: Add camera ACPI configurationDaniel Kang
Add camera ACPI configuration for Ripto/Volteer BUG=None BRANCH=None TEST=Build and boot Ripto or Volteer. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/volteer: Enable PD_MCU devicePrashant Malani
This is required for PD notifications on the cros_ec driver. BUG=b:150649744 TEST=Boot volteer with this patch and verify that PD notifier events are being generated. Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entriesMichał Żygowski
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23mb/tglrvp: Update Audio AIC settings for Tiger LakeSrinidhi N Kaushik
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23src/mb/intel/tglrvp: Fix board config flag for TGL-UP4 camera ACPIDaniel Kang
Camera ACPI had an incorrect board config flag for TGL-UP4. BUG=None BRANCH=None TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/dedede: Update SPD index for waddledeeKarthikeyan Ramasubramanian
Micron memory part uses SPD Index 0. BUG=b:152005386 TEST=Build the mainboard. Change-Id: I990a95b13d636148f0f922fd5c6d4e489d35ed2c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20mb/google/dedede Add Audio support for waddledooAamir Bohra
1. Configure Audio GPIOs. 2. Set i2c4 configuration. 3. Update PCH HDA configuration TEST=Verify codecs gets listed with aplay -l command. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-20drivers/generic/max98357a: Allow custom _HID from configAamir Bohra
Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-onlyAngel Pons
Change-Id: I005bf205142d4d8c5e12378f33d2100d278fa174 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons
Change-Id: I78f06b54a6a03d565cf86f1d7bdf37965c3f6ad0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Remove copyright statementsAngel Pons
They are already in AUTHORS. Change-Id: I315c0c57babfa239e3d7c501a4183b8996999e6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/google/nightfury: Update overridetree.cbSeunghwan Kim
Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury BUG=none BRANCH=firmware-hatch-12672.B TEST=built and verified touchpad and touchscreen worked Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-20mb/hp/z220: Fix VGA graphics initPatrick Rudolph
The VGA port has the DDC on port B. Select the correct Kconfig and fix graphics init failing on VGA. Tested on HP Z220, libgfxinit reports success and SeaBIOS is displayed on the connected VGA monitor. Change-Id: Ie5ec1a2d4606a21e1dc4217ff6fefe5ee35ac543 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-19mb/asrock/b85m_pro4: Add new mainboardAngel Pons
This is a µATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Working: - All four DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI and DVI - Intel GbE - All PCIe ports - Both PCI ports behind the ASM1083 PCI bridge - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux Not working: - PS/2 keyboard (detected as mouse) Untested: - The other audio jacks - S/PDIF - VGA - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - Parallel port Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18src/mainboard/g/octopus: Enables GMM in the devicetree for octopusFranklin He
Adds GMM into the baseboard of Octopus For GLK, PCI device 3 is GMM according to Document#: 569262(Glk EDS Vol-1 rev2-7) Related to Gerrit review 39579 BUG=b:151115705 BRANCH=None TEST=Flashed final image on Chromebook Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd Signed-off-by: Franklin He <franklinh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-18mb/google/dedede: Support integratred BT enumerationAamir Bohra
The integrated BT is routed via USB2 port 8, add USB configuration to support integrated BT enumeration. Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-17src/mb/intel/tglrvp: Update camera ACPI configurationDaniel Kang
* Change power sequence to make it closer to ov8856 sensor data sheet version 2 * Handle different PWREN GPIO pins for up3 and up4 * Add link frequencies definitions to sensor side * Clean up format BUG=None BRANCH=None TEST=Build and boot TGLRVP U or Y. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39529 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASLRizwan Qureshi
Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17mb/google/octopus: Add custom SAR values for Foob360Peichao Wang
Foob360 would prefer to use different SAR values. Since Foob360 sku id is 9. BUG=b:149362272 BRANCH=octopus TEST=build Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-03-17mb/purism: remove duplicate ACPI power buttonMatt DeVillier
These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Same change was applied to all google mainboards in CB:27272 which contains more detail. Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17mb/google/dedede: Add waddledee variantKarthikeyan Ramasubramanian
Add initial support for waddledee variant board. BUG=b:151576904 TEST=Build the mainboard and variant board. Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-16mb/intel/tglrvp: Enable ISH driver and register firmware nameli feng
BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3, then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin check "dmesg |grep ish", it shows: ish-loader: ISH firmware intel/tglrvp_ish.bin loaded cros_ec_ishtp: Chrome EC device registered Those means shim loader in coreboot has loaded ISH firmware, and firmware is running successfully. Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16mb/51nb/x210: correct battery ACPIMatt DeVillier
The X210 EC reports battery values in broken mAh. These have to be adjusted by 10000 * DGVO, as documented in https://github.com/torvalds/linux/blob/master/drivers/acpi/battery.c. Taken from https://github.com/harrykipper/coreboot, commits 2f68f138adb25605e5715896636cf33f6de5bd95 c1c72cc43708a6647f263a767c39cf3072908e20 Change-Id: Ie097272443b18b16c3937034f874d3b5a6bdd62a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39142 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16mb/51nb/x210: update devicetreeMatt DeVillier
- Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Improve comment for M.2-2230 USB port (BT) Parts derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16mb/51nb/x210: add libgfxinit supportMatt DeVillier
Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Test: build/boot x210, test eDP, MiniDP, VGA outputs Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16mb/51nb: Add support for the 51nb X210Matthew Garrett
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different All hardware appears to work as expected, although the SD reader is untested. Signed-off-by: Matthew Garrett <mjg59@google.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-15mb/google/kahlee/nuwani: support new Elan touch panel for NuwaniTommie
This is new Elan touch screen IC, which includes touch panel and USI pen. BUG=b:151514167 TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com> Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/asus/p8z77-m_pro: Use uppercase for *PRO*Paul Menzel
Consistently use the official uppercase spelling. Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3Srinidhi N Kaushik
Enable CNVi in devicetree and add gpio pad configs for CNVi BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/google/hatch: Create palkia variantKane Chen
Add Palkia as a variant of Hatch. BUG=b:150254194 BRANCH=none TEST=none Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/google/volteer: Use generic SPD filesNick Vaccaro
Volteer uses 4 bits (hardware straps) to indicate what memory configuration the board is populated with (i.e. which SPD file to use for the populated memory). This allows for only 16 different SPDs for supporting Volteer and all future variants of Volteer. Currently, each memory chip needs its own SPD file, so we can only support 16 different memory chip options for Volteer and all of its variants. Generic SPD files are just SPD files that have been stripped down to contain only fields that are important for the memory controller (strips out items like vendor info, for example). Using generic SPD files allows for more than 16 different memory options given it's no longer a 1-to-1 mapping as similar memory modules from different vendors can share the same generic SPD file. BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB of memory. Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/google/dedede: Configure WLANKarthikeyan Ramasubramanian
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-14mb/google/dedede: Add BT Disable GPIO configurationKarthikeyan Ramasubramanian
Disable the BT module in bootblock and enable it in ramstage. This allows for loading the BT firmware during reboot. TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/google/drallion: Enable GEO SAREric Lai
Enable GEO SAR function. BUG=b:150347463 BRANCH=drallion TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/intel/tglrvp: Update GPIO settingWonkyu Kim
Update GPIO reset type from PLTRST to DEEP. DEEP setting is more conservative for S3/S4/S5. Detail information is bug. BUG=b:151305120 TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-13mb/google/volteer: Enable Audio DSP UPDSrinidhi N Kaushik
Provide settings for configuring the link between HD-Audio controller and display unit for purposes of HDMI/DP Audio playback. BUG=b:144708516, b:148385924 TEST=none Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-13mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on PuffEdward O'Callaghan
Early ec sync needs to be disabled for EFS2 to function. BUG=b:151115320 BRANCH=none TEST=none Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-12mb/google/dedede: Enable trackpad supportPandya, Varshit B
1. Configure trackpad interrupt GPIO. 2. Set i2c0 configuration. 3. Add trackpad ACPI support. TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz on trackpad operation. Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-12mb/google/hatch: Create nightfury variantraymondchung
Create new variant and build for nightfury. BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-03-12mb/google/volteer: configure L1Substate for PCIeWonkyu Kim
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround. Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330 BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-11mb/google/dedede: Add ACPI configuration for USB portsKarthikeyan Ramasubramanian
Enable USB ACPI driver. Add ACPI configuration for all the USB ports. Since one of the USB ports is used for Bluetooth configure the reset_gpio used by that port. TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 04:25:47 +0000