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2020-09-21volteer: set GSPI CS to deasserted by defaultCaveh Jalali
This sets the state of GSPI chip select to 1 (deasserted) as applied by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS mode manual in the SerialIoGSpiCsMode section which means we need to explicitly configure CS to deasserted in the SerialIoGSpiCsState section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We were running into problems where the normal expected CS toggle sequence to wake up CR50 did not work because CS was already asserted when it was expected to be deasserted, leading to TPM timeouts. BUG=b:168090038 TEST=booted on volteer, no more "TPM flow control failure" messages; verified fingerprint enrollment still works. Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/google/volteer: Add firmware configuration for MAX98373_ALC5682I_I2S_UP4Frank Wu
Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor: > AUDIO=MAX98373_ALC5682I_I2S_UP4 ectool cbi set 6 0x00000400 4 2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-21mb/google/volteer: fw_config: Add fields for keyboard featuresDuncan Laurie
Add newly defined fields for presence of keyboard backlight and number pad to the firmware configuration table. We don't have a need to use these in coreboot (yet) but this keeps the bit definitions in sync. BUG=b:166707536 TEST=abuild -t google/volteer Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-20mb/system76/lemp9: move LPC options to the devicetreeMichael Niewöhner
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: correct CBFS_SIZEMichael Niewöhner
The BIOS region size is 0xc00000, not 0xa00000. Correct this. Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-20mb/system76/lemp9: enable SATA ALPM capabilityMichael Niewöhner
Enable SATA Link Power Management capability to be able to save power. TEST: /sys/class/scsi_host/host*/link_power_management_policy exists. Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: drop disabled options from devicetreeMichael Niewöhner
Drop all options with zero-value, since they already default to 0. Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/google/zork: update morphius dptc clamshell/tablet mode settingKevin Chiu
clamshell/tablet: Slow_ppt_limit(W) 20 Fast_ppt_limit(W) 24 Slow_ppt_time_constant 5 Stapm_time_constant 200 Sustained_power_limit(W) 12 clamshell: Temperature limit(C') 100 tablet: Temperature limit(C') 70 BUG=b:157943445 BRANCH=zork TEST=1. emerge-zork coreboot 2. change mode and check "thermctl_limit" will change Change-Id: I1eda1411766e446b673046236f7cc4015696521f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-19mb/system76/lemp9: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19mb/up/squared: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: Icf62a73ee568d9369c53bd767bd4cfb736ea76f1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19apollolake boards: Enable CSE in devicetreeSubrata Banik
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-18trogdor: Move EN_PP3300_DX_EDP for CoachzJulius Werner
This patch updates the display power enable GPIO which moved from 30 to 52 for Coachz. Veterans of this project know that there's no point trying to ask *why* this change was necessary -- the pins move in mysterious ways and all we can do is watch and wonder. Pin 30 is now used for a new camera reset GPIO... surely, there must have been some excellent reason why that pin couldn't just have become pin 52 instead. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-18mb/google/octopus/variants/fleex: support LTE power sequenceEric Lai
GPIOs related to power sequence are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18mb/google/volteer: Remove redundant GPIO decls in EldridTim Wawrzynczak
GPP_A19 and GPP_A20 are already declared as NC in the baseboard. Change-Id: I02f5751a70b51a197320b865d18da3a4ffeb87f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45485 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18mb/google/volteer/eldrid: Add option to enable WiFi SAR configsMalik_Hsu
This change adds a user selectable option to enable all WiFi SAR configs that apply to volteer BUG=b:168169690 TEST=1. cros-workon-volteer start coreboot-private-files-baseboard-volteer 2. USE="project_eldrid" emerge-volteer chromeos-config coreboot-private-files-baseboard-volteer 3. check wifi_sar-eldrid.hex in coreboot-private/3rdparty/blobs/baseboard-volteer Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18superio/nuvoton: Inline `nuvoton_hwm_select_bank`Angel Pons
There's no need to place a single-line function in its own compilation unit, and then guard it behind a Kconfig symbol. This also allows using this function in stages other than ramstage. Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42130 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: update power limitsJeremy Soller
Tested on lemp9, power limits are adjusted from the previously low values to the values the thermal system can handle. This was determined by increasing the values and running the system at 100% CPU utilization until thermal throttling occured and the chassis temperature became uncomfortable. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I5e176e9d98376f8e2dc415e4397efc456869e72d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43624 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: disable PCH DMIC, which is not wiredMichael Niewöhner
The microphone is wired to the audio codec, not to the PCH. Disable the DMIC interface. Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45133 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: skip FSP init of UART2Jeremy Soller
This UART is already initialized by coreboot for the console, it does not need to be initialized by the FSP. Tested on lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
This allows us to drop some casts to uintptr_t around the tree. The MCHBAR32 macro still needs a cast to preserve reproducibility. Only the native raminit path needs the cast, the MRC path does not. Tested with BUILD_TIMELESS=1, these boards remain identical: - Lenovo ThinkPad X230 - Dell OptiPlex 9010 - Roda RW11 (with MRC raminit) Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
RCBA is located in the PCH. Replace all instances with the already-defined `DEFAULT_RCBA` macro, which is equivalent. Change-Id: I4b92737820b126d32da09b69e09675464aa22e31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: move HDA options into devicetreeMichael Niewöhner
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS basedShreesh Chhabbi
platforms BUG=b:145958015 TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin. Cq-Depend:chrome-internal-review:3249528 Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-17mb/google/volteer/variants/eldrid: Configure DP_HPD as PAD_NCnick_xr_chen
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:165893624, b:168090618 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246 Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/google/zork: Add dptc interface support for morphiusChris Wang
Add dptc interface in devicetree for morphius. Set the STAPM parameters for tablet mode: dptc_enable = 1 dptc_fast_ppt_limit = 24000 dptc_slow_ppt_limit = 20000 dptc_sustained_power_limit = 6000 BUG=b:157943445 BRANCH=zork TEST=Build. check the setting changed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16mb/google/dedede: Replace static Camera ACPI by driver for WDooPandya, Varshit B
This change updates devicetree to enable SSDT generation for world facing camera and user facing camera of Waddledoo. Also reverts DSDT changes related to both the camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-09-16mb/google/dedede/var/madoo: Enable keyboard backlight featureIan Feng
This enables the keyboard backlight feature in ACPI for madoo. BUG=b:167943993 TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds '. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I11531699cb650b96becae5c1bec9f89c48b6bea0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-16zork/var/ezkinil: Fix Touchscreen doesn't work on v3.6x rework boardLucas Chen
The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed. BRANCH=zork BUG=b:168580357 TEST=Check Touchscreen function work Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16trogdor: invoke new watchdog function before qclib runsRavi Kumar Bokka
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15mb/intel/jasperlake_rvp: Fix wrong comments for ECTSubrata Banik
Disable -> Enable Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-15mb/google/dedede/var/magolor: Add touch screen devicesRen Kuo
add the magolor touch screen ctrl devices: 1)elan 6915 2)elan 5012 3)raydium RM32680 BUG=b:166711761 BRANCH=None TEST=build firmware and verify the touch functions on DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15mb/google/zork: Fix FPMCU_INT_L configurationFurquan Shaikh
Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge triggered. Also, we are using GEVENT for wake from fingerprint and not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables does not need to be set to indicate wake for the IRQ. This change updates GPIO table to configure the pad as level triggered and drops the wake attribute for irq_gpio in overridetree. BUG=b:165612778 BRANCH=zork TEST=Verified that fingerprint still works in S0 and to wake device from S3. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14src/mainboard: Remove unused include <device/pnp_ops.h>Elyes HAOUAS
Change-Id: I278fb20aa176bb09f1ff135fdfd732f0096d3808 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14mb/amd/olivehill/bootblock.c: Add missing <arch/io.h>Elyes HAOUAS
Change-Id: I75ea4fc71cf22e5ad547329db2451342cee528b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpdRavi Sarawadi
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Delbin board. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-14mb/google/octopus/variants/fleex: Add G2Touch touchscreen supportJohn Su
BUG=b:167297664 BRANCH=octopus TEST=build fleex, and check touchscreen can work Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980 Reviewed-by: Justin TerAvest <teravest@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/dedede/var/boten: Add audio configurationKarthikeyan Ramasubramanian
Add configuration for ALC5682 headphone jack and ALC1015 speaker amplifier. Also turn on the HDA PCI device. BUG=b:161667665 TEST=Build the boten board and verified the audio functionality. Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/ocp/deltalake: Drop redundant `select FSP_CAR`Angel Pons
This is selected by Xeon SP Kconfig already. Change-Id: If1ef7f86b27d7be74912c9ad1f9c1efbda6233e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-09-14mb/google/volteer: Fix GPP_E12 definitionCaveh Jalali
GPP_E12 should not be defined in the baseboard as its use is determined by the variant. For legacy reasons, we still have GPP_E12 defined in early_gpio but should not. Malefor and volteer* have the same GPP_E12 definition, but that is a misconfiguration. I think that was a copy-paste that slipped through the reviews. BUG=b:157597158 TEST=volteer2 boots to the OS Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14mb/google/volteer/var/voxel: Update DPTF parameters and TCC offsetDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14mb/google/volteer: Refactor baseboard devicetreeTim Wawrzynczak
Clean up the DPTF section of the baseboard devicetree; this makes overrides simpler, as not necessarily all of the fields need to be overridden. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20WSumeet R Pawnikar
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/volteer: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1432491 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ife38b1450451cb25e5479760d640375db153e499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/volteer: Enable EC software syncDavid Wu
Enable EC software sync for terrador and todor BUG=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-13soc/amd/picasso/chip: fix typo in acp_pme_enableFelix Held
That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12mb/ocp/deltalake: Enable TPM2Christian Walter
Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-11mb/msi/ms7721: Use PNP_IDX_EN instead of magic numberElyes HAOUAS
Change-Id: Ica66ad6da61376f64f9d24de015f84d250327d66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11mb/ibase/mb899: Use 'PNP_IDX_*' macros instead of magic numberElyes HAOUAS
Change-Id: I1e543f8ff701fa20eaaee601ef54f0b056e61909 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 21:53:34 +0000