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This option is not mainboard-specific, and should be user-visible.
Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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To make the L140CU able to be selected by other OEMs, use
BOARD_CLEVO_L140CU_BASE for OEM independent options.
BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any
OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the
baseboard.
Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST#
BUG=b:182100027
TEST=ls /dev/nvme*
Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to
make clear that this option represents the baseboard.
Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.
Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I98d806ebf126522689b2c101b75add733825fcf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Hook up FSP-M configuration on mainboard level instead of variant level
being able to do common configuration there.
Also, hook up variant romstage.c on mainboard level for variant
specific configurations.
Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to
set it here.
Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC
software sync needs to be enabled in payload once the EFS2 requirements
are met.
BUG=b:185277224
TEST=Build.
Cq-Depend: chromium:2829948
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.
BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.
Cq-Depend: chromium:2832032
Change-Id: I921dc5c814e5187dce283eeff43075b59885723a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS
is selected, so non-ChromeOS targets use the default x86 FMAP.
Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Sync from guybrush.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The
concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has
a voltage rating of 3.3 V. The schematics has been updated to bridge the
gap. So enable the speaker amplifier by default and add a gpio override
table to disable the speakers before board version 2.
Also update the codec ACPI HID name for the kernel machine driver to
probe the codec successfully.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state
is high.
Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.
Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.
This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.
This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO config based on review of latest schematics:
- LAN/WLAN reset lines are NC
- SDIO lines configured via GPP_G0-G7
- DMIC lines are wired directly to codec, not PCH, so GPP_D17-20
are set to NC
- Pads GPP_H0-H3 are configured for I2S2
- Pads GPP_H7-H9 are straps for board revision, so treated as GPI
- CPU_C10_GATE# is NC
- PWRBTN# does not need an internal pull-up
- GPP_C20-23 are configured for M.2 UART
- SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups
- GPP_C6/C7 set to I2C1 for future use
- GPP_E15 changed from SCI to SMI, edge triggered
Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When a pad is configured as NC, it is set as a GPI with both
TX and RX disabled, and as the pad is internally disconnected,
no pull up or pull down is needed.
Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CRFP in devicetree and configure GPIOs.
BUG=b:182201937
BRANCH=None
TEST=Boot into OS and confirm FPMCU is responding.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add the SATA device to the device tree so it may be found
when trying to write SATA registers. Otherwise, it fails
on "requests hidden 00:17.0 PCI: dev is NULL!"
Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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MPTS is currently not executed by the AML interpreter.
Use Method (\\_SB.MPTS) instead of
Scope (\\_SB)
Method (MPTS)
ScopeEnd
Tested on Prodrive Hermes. MPTS is now executed at S5.
Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
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Add ACPI code to enable the backlight when we enter the OS.
BUG=b:184198808
TEST=Backlight enabled in the OS
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I33a5f177affc3f13d091a85073499b7283f54ada
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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support audio AMP selection with fw_config.
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add AUDIO_AMP ports bit field in devicetree.
UNPROVISIONED 0
MAX98360 1
RT1015_I2C 2
RT1015P_AUTO 3
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CBFS size equals flash size, leaving no space for descriptor and ME.
Reduce CBFS_SIZE.
BUG = N/A
TEST = Build and boot Portwell M107
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Ida5a248edf4f602c4a106ae29d706e732ef8454f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TPM_INIT_RAMSTAGE needs to be enabled for measured boot only
configuration.
Remove TPM_INIT_RAMSTAGE disable.
BUG = NA
TEST = Boot possible combinations of VBOOT, measured boot and vendorcode
security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I91bde691d445d4210429c928e90e16653092f1cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Modify GPIO_D22/D23/E11 configuration for P-sensor
BUG=b:185214363
BRANCH=dedede
TEST=built storo firmware and verified P-sensor function
Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The darp5 has several GPIO differences to the galp3-c, which are already
accounted for in gpio.c.
Change-Id: I951e86e53e9c47b9f3038927f44e505d37200c26
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add uart controller to chipset.cb and leave it off by default.
Turn uart0 on for console for mainboards.
BUG=none
TEST=builds and boot into OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping
BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly
Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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The patch enables ALC711 over SNDW0.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add log to show the codec has been disabled.
BUG=b:185193926
TEST=cbmem -c | grep disabled, can find the codec name
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ce7e435ce73beb2a5cbf5883905554227b1989b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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BUG=b:185397933
TEST=boot guybrush and no longer see tis_plat_irq_status warnings
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is the same as zork.
BUG=b:184126844
TEST=Boot guybrush in developer mode and switch to normal mode.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=none
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This include provides the GPIO_x definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12a0d95f79658f3852132876e92c389b715f3001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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platform_descriptors.h is unrelated to the contents of baseboard/gpio.h
where it was included, so move the includes to the files where it is
actually needed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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amdblocks/gpio_defs.h provides the definitions of GEVENT_x.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I353f0d241391dd1122c85866a74984b95ed54770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52305
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that
definition in all places in the mainboard code instead of a mix of the
board specific define and the SoC's GEVENT number define.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Enable CRFP power control in gpio table. RST needs to drive low
before PWR enable. Since reset signal is asserted in bootblock,
it results in FPMCU not working after a S3 resume. This is a known issue.
BUG=b:181377402
BRANCH=None
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows using the internal speakers of the oryp5.
Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].
[1]: https://github.com/system76/smart-amp
Change-Id: I148f18ff3e754d913bdf907121b103c6de02ffc3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47962
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add LTE modem to devicetree
Configure GPIO control for LTE modem
BUG=b:178092096
TEST=Built image and verified with command modem status
Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:185084331
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ie982741cb7b328623cf27f41c31f819e8cdb7bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:175364713,b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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