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2018-08-03mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driverMatt DeVillier
These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03mb/google/poppy/variants/atlas: Apply correct AC/DC loadlinesGaggery Tsai
This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b:111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27788 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cheza: Deassert USB hub reset pinJulius Werner
This patch makes sure we deassert the USB hub reset pin so the hub will work with the next board revision that drops the external pull-up. (Actual USB support comes in a later patch.) Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27790 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02cheza: Add board ID, RAM code and SKU IDJulius Werner
This patch adds the required callbacks to read all strapping IDs on Cheza. Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02mb/lenovo/x1_carbon_gen1: add vbtAlexander Couzens
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware. Thanks to Igor Lee. Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-02mb/google/poppy/variants/nami: Tune Fan speedSumeet Pawnikar
Tuning of fan speed for different temperature values. Earlier while running few benchmarks, fan was always getting on and starting at higher speed. With this change fan will start with lower speed and slowly speed gets increased if temperature continue going high. Thermal team provided these data after fine tuning of fan speed. BUG=None. TEST=Verified on Nami running with different benchmarks and observed fan speed. Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02mb/google/poppy/variants/nami: Enable mbox command for ISL VR c-state issueShelley Chen
There is a potential IMVP8 issue for KBL that affects Intersil VRs Nami is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:112081534 BRANCH=None TEST=Build and boot Nami Verify that suspend/resume and consecutive reboots are working Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-02google/banon: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/edgar: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 2319742 and 3b59fb2 [Edgar: Add Micron MT52L256M32D1PF-107 SPD data] [Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data] Supported 2nd source Hynix, Micron, and Nanya memory. TEST=Built and used mosys command by "mosys -k memory spd print all" Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579 Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0 Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Configure WLAN_CLKREQ as GPIO and always assert lowMatt DeVillier
Adapted from chromium commit adcb858 [cyan: Configure WLAN_CLKREQ as GPIO and always assert low] This is a workaround for issue b/35648315 as proposed by Intel to ensure that WLAN_CLKREQ always stays low. BUG=b:35648315 Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1055652 Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Tested-by: Rajat Jain <rajatja@chromium.org> Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mask Audio IRQ on bootMatt DeVillier
Adapted from chromium commit cf18ab6 [Strago: mask Audio IRQ on boot] Do not start with audio interrupt unmasked; this causes interrupt storms on newer kernels that no longer mask all interrupts when initializing Cherryview pincontrol driver. TEST=Boot various cyan boards with kernels 3.18 and 4.14; verify everything works. Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894688 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mark GpioInt() resources as PullDefaultMatt DeVillier
Adapted from chromium commit 3750e09 [Strago: mark GpioInt() resources as PullDefault] coreboot considers GPIO resources first-class citizens and initializes all pads according to their intended use, with necessary pull settings applied. Therefore let's use PullDefault as pull qualifier in AML, letting the kernel know that it should not attempt to alter pull settings when using GPIOs. TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices. Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/898259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27760 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggeredMatt DeVillier
Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: do not hardcode virtual interrupt numbersMatt DeVillier
Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02mb/google/octopus: Enable EC SW sync for allJustin TerAvest
Since this works on Yorp and Bip, we should enable EC SW sync for all known boards so that it doesn't get forgotten. BUG=None TEST=None Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27755 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01mb/google/poppy/variant/nami: Overwrite AC/DC loadlinesGaggery Tsai
This patch adds a function to overwrite AC/DC loadlines for differnt projects. BUG=b:111761175 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump AC/DC loadline settings. Tested on Vayne and Akali. Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-31mb/google/octopus: add lpddr4 skus for new memory sourcesnickchen
Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046. BUG=b:111964159 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/google/octopus: Enable EC SW sync for fleexJustin TerAvest
This never got enabled for fleex; we should enable this to make it easier to have updated EC firmware. With this commit, here's the relevant console messages: sync_one_ec: devidx=0 select_rw=4 update_ec: Updating RW(active)... Trying to locate 'ecrw' in CBFS update_ec: image len = 137580 EFS: EC is verifying updated image... send_packet: CrosEC result code 1 EFS: EC doesn't support EFS_VERIFY command vboot_hash_image: No valid hash (status=0 size=0). Compute one... print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd Trying to locate 'ecrw.hash' in CBFS sync_one_ec: jumping to EC-RW send_packet: CrosEC result code 12 EC returned from reboot after 27753us BUG=b:112038021 TEST=Successful boot after EC update via sync Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-31samsung/stumpy: Add support for libgfxinitMatt DeVillier
Add support for libgfxinit Test: boot stumpy, verify all outputs operational prior for pre-OS display Change-Id: Ia720814c2225502316de5c5e9639c67df65a2ed0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-31mainboard/google/kahlee: Update VBIOS imageRichard Spiegel
The careena board requires a different setting within VBIOS in order to pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS. CQ-DEPEND=CL:1153080 BUG=b:111673328 TEST=Verify, via SOME unspecified method, that the new vBIOS is built into the Grunt/Careena ROM files. Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27643 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/amd/gardenia: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove IMC files and functions from gardenia. BUG=b:111780177 TEST=Build gardenia Change-Id: I570b7f8e364b0c2937592590cc033d5a6c9fade0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27650 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/stout: Use new PMBASE APIPatrick Rudolph
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mb/samsung/lumpy: Use new PMBASE APIPatrick Rudolph
Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/link: Use new PMBASE APIPatrick Rudolph
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/parrot/smihandler: Use new PMBASE APIPatrick Rudolph
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mb/google/poppy/variants/atlas: Add new Nanya memory optionTim Chen
- add Nanya NT6CL256T32CM-H1 to memory strapping table BUG=b:111906760 BRANCH=none TEST=none Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30mainboard/google/nocturne: simplify camera power referencesMatt Delco
This change primarily moves the PowerResource up to a more common scope so that the _PRx references are simpler. The ^ scope modifier isn't well supported everywhere amongst OSes and drivers. Windows 10 will BSOD early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could not find the object referenced by a _PRx) with the way things are currently laid out). I've also not seen a firmware outside of coreboot that tries to reference count _ON and _OFF. Isn't it up to the OS to deference count, and whatever it tells ACPI is what should happen (i.e., on means on and off means off)? Some of the _UIDs are also duplicated. This change makes them unique. A few cosmetic changes are made so that diffing cam0.asl against cam1.asl has fewer extraneous differences. Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30google/caroline: Change debounce time for jack insertion and ejectionMatt DeVillier
Adapted from chromium commit 7633daa [caroline: Change debounce time for jack insertion and ejection] We are using max debounce time. During this time line, MICBIAS will be zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE) We need to reduce this time to below 100ms for caroline device. BUG=b:79559096 TEST=see there is no more irq before jack insertion/ejection irq complete Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1143109 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27659 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30google/kukui: Enable eMMC in bootblock.Hung-Te Lin
On kukui board, the eMMC is routed to EC for boot ROM emulation when loading bootblock, and should be set back to real eMMC as early as possible after bootblock is loaded. BUG=b:80501386 TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled. BRANCH=None Change-Id: Ifefb2e26ed048c38595907cc0875757410129828 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable FPMCU powerNick Vaccaro
Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable ec host event wakeNick Vaccaro
Enable nocturne to wake from lid attach/detach events. BUG=b:111803637 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne wakes from suspend on a lid attach/detach event. Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27649 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/nautilus: Remove obsolete fieldsAlan Chiang
Some fields were only required during early stages of IPU3. Remove some fields that aren't used for the current version of IPU3. BUG:None TEST=Launch camera app and check if it works properly. Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d Signed-off-by: Alan Chiang <alanx.chiang@intel.com> Reviewed-on: https://review.coreboot.org/27617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30mb/cavium/cn8100_sff_evb: Compile devicetree for LinuxPatrick Rudolph
Compile the linux devicetree using dtc and add it to CBFS. Change-Id: I8a98ed7b128f65a6e0109963dbabca91563a315c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30mb/google/octopusi/variants/bip: Fix unused pins and those with external ↵Furquan Shaikh
terminations For unused pins, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 TEST=On Bip, flashed image and verified that it boots to OS. Also executed a few suspend resume cycles. Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/27634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30mainboard/opencellular/rotundu: Add FMAP supportzaolin
* Add 8M and 16M fmap configurations. * Fix kconfig selects. * Add vboot options and fixes Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/25084 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nautilus: Set GPP_D21 to high as defaultSeunghwan Kim
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means LTE tx power is backoff mode as default. We would set GPP_D21 to high to change LTE tx power to normal mode as default. BUG=None BRANCH=poppy TEST=Verified default LTE tx power mode is normal mode as default Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nami: Fix fan is always ONJohn Su
Add the new setting for fan performance state. BUG=b:111860513, b:11865138 TEST=Fan do not run below trip point Change-Id: I894460b8b418217e2477608094c37018437cbb78 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-29mb/google/octopus: Perform EC init before bootblock gpio configurationFurquan Shaikh
A variant might talk to the EC to get board id in order to identify the right GPIO configuration. Thus it is important to ensure that the LPC IO windows are configured before this. This change moves the call to perform EC init before configuring bootblock GPIOs. BUG=b:111933657 TEST=Verified that reading board id does not fail on phaser. Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27671 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/opencellular/rotundu: Enable TPM 1.2 supportPhilipp Deppenwiese
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28mainboard/opencellular/rotundu: Add supabrck EMMC supportPhilipp Deppenwiese
Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28opencellular/rotundu: Introduce variants for OCPhilipp Deppenwiese
* Add Supabrck v1 variant * Modify rotundu base board Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC errorKevin Chiu
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27657 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27mb/lenovo/*/devicetree: Add support for WWAN detectionPatrick Rudolph
Add support for WWAN detection on SNB/IVB boards that have schematics or are available for testing. Tested on Lenovo T430. Change-Id: Ie96b2593971d49703eb747ab19f512be890d9c12 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20984 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27google/kukui: Add SPI NOR supportTristan Shieh
This patch sets SPI flash related configs and inits SPI bus 1 to support SPI NOR flash. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-26google/caroline: Add missing audio codec infoMatt DeVillier
Add audio codec definitions in devicetree, which were accidentally dropped when upstreaming Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio. Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27626 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26google/caroline: Fix I2C2 ACPI device definitionMatt DeVillier
Remove duplicate FMCN package for I2C2, since already generated by the devicetree-linked generic i2c driver. This fixes an ACPI parsing error which resulted in the touchpad and touchscreen being non-functional. Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and touchscreen functioning properly, no ACPI errors in dmesg. Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26mb/google/octopus/variants/phaser: Provide override GPIO configFurquan Shaikh
This change provides override GPIO table for variant phaser depending upon the board id. Additionally, early_gpio_table is also provided for phaser since EN_PP3300_WLAN needs to be handled differently based on board id. BUG=b:111743717 TEST=Verified that GPIO configuration for the override GPIOs is different than before with this change. Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 22:20:29 +0000