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2020-10-20mb/google/volteer/var/terrador: Configure board specific DPTF parametersDavid Wu
Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20mb/google/volteer/variants/lillipup: add generic SPDsNick Vaccaro
Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mb/google/dedede: Add P-sensor for Botenalec.wang
Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/google/dedede: add PEN for Botenalec.wang
Update devicetree of boten that enable stylus BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFSAngel Pons
I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20mb/google/asurada: Init dram in romstageHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/siemens/chili: Add Chili variantNico Huber
This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/siemens/chili: Add new mainboardThomas Heijligen
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19mb/google/octopus/variants/ampton: Add G2Touch touchscreen supportJames Chao
BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-19superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons
There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency"Rob Barnes
This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51. Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible. TEST=Boot Dalboz BUG=b:159823235, b:169940175 BRANCH=zork Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-19mb/google/dedede/var/waddledee: Enable GPIO based I2C MultiplexerKarthikeyan Ramasubramanian
The camera sensor component chosen for UFC and WFC have an address conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also configure the GPIO that is used as select line. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19mb/google/volteer: Enable USB4 retimer driverDuncan Laurie
Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/google/kukui: Support SKU from camera EEPROMHung-Te Lin
To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen
Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/purism/librem_skl: Clean up FSP-M RCOMP settingsAngel Pons
There's no need to use static functions to fill these settings in. Also, add missing include for <stdint.h> and initialize `mem_cfg` in one line. Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46252 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/zork/var/vilboz: update dptc stapm timeJohn Su
Update dptc setting: Stapm_time_constant 1400 BUG=b:170696020 BRANCH=zork TEST=emerge coreboot and check "Stapm_time_constant" Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-17mb: AMD CIMx boards: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17AGESA mb: Replace tab with space in macro definition for consistencyPaul Menzel
With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner
This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-16mb/google/zork: disable eMMC per FW_CONFIG for berknipKevin Chiu
Berknip has SSD/eMMC SKU, we should turn off eMMC　if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-16mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik
This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/google/volteer: Disable HybridStorageMode for volteer baseboardShaunak Saha
HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/adlrvp: Add ADL-P mainboard ASL codeSubrata Banik
Add required ASL files into dsdt.asl TEST=Dump and disassemble DSDT and verify all ACPI devices are present. Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/adlrvp: Add ADL-P ramstage mainboard codeSubrata Banik
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/purism/librem_skl: Drop DQ and DQS byte mapsAngel Pons
These settings are not necessary for DDR4 and can be dropped. Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-14mb/google/dedede/var/madoo: Update DPTF settingJohn Su
Add tcc, critical, passive policy, and pl values from thermal team. BUG=b:169215576 TEST=build and verify by thermal tool Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-10-14mb/intel/tglrvp: Enable Pcie WWAN m.2Bora Guvendik
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration. BUG=none TEST=Boot to OS, check WWAN functionality Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/zork: Enable wake on wireless lanRob Barnes
Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up BRANCH=zork Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)Tony Huang
Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()Elyes HAOUAS
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniformElyes HAOUAS
Make output AML file name uniform. Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13volteer: Create elemi variantWisley Chen
Create the elemi variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:170604353 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELEMI Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-13mb/google/zork: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/asrock/h110m/romstage.c: Drop invalid SPD addressesAngel Pons
Pictures on the internet show that the Asrock H110M-DVS (Kconfig.name) only has two DIMM slots. Since the vendor's website advertises support for dual channel memory, drop the SPD addresses for the second slot of each channel. The result is the same as several other two-slot boards. Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/asrock/h110m/romstage.c: Correct FSP-M UPDsAngel Pons
The DQ and DQS byte maps do not apply to DDR4 configurations, and the RCOMP resistor and target values are not correct for SKL-S (or KBL-S). Drop the byte maps and use RCOMP values for the correct platform type. RCOMP resistor values for all non-socketed platforms are listed in the Platform Design Guide, and also appear in schematics. For SKL-S, the RCOMP resistors are on the CPU and their values have been confirmed by measuring them on an i5-6400, and match the PDG values for SKL-H. RCOMP target values can be guessed from Intel Document #573387 and some of them are also present in datasheet volume 1, under DC specifications. Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/ocp/deltalake: Update SMBIOS type 9 informationJingle Hsu
Update Slot Designation strings and add SSD0_M2_Boot_Drive for config A. TEST="dmidecode -t 9" to verify the results are expected. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/46125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13mb/google/puff/var/dooly: Update devicetree for audio and display configurationTony Huang
1. Add speaker amplifier ALC1015 2. Enable dmic+ssp registers for speaker and camera DMIC 3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree to remove unused devicesTony Huang
Remove unused device in Dooly no SD card reader no built-in LAN BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree for USB configurationTony Huang
Dooly has USBA*2 and USBC*2 BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update GPIO table for project changeTony Huang
Override unused device SD card reader, built-in LAN ALC1015 speaker amplifier SPK_AMP_ON Update touchscreen/lvds gpio pin BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I6f4d0bf9adc1cce4942a16675a072ffea00bd2e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-12 19:55:54 +0000