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2018-09-28soc/intel/cannonlake: Update UPD from device switchLijian Zhao
Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-26mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum valueSumeet Pawnikar
Increase power limit1 maximum value from 5W to 7W. This value as per recent measurement on closed system which shows better performance results. BUG=None TEST=Build and tested on Nocturne system. Performance tests show better results. Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-26mb/google/poppy/variants/nocturne: Add tdp_pl1_override valueSumeet Pawnikar
Add tdp_pl1_override value as 7W. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
2018-09-26mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
The previous does not work well enough when testing with high ambient temperature. Update DPTF settings to make it work better. List of tweaks: 1. Raise DRAM Critical temperature from 48C to 55C Note that there are mechanisms in EC that complement this because of DPTF limitation that we can't have multiple passive temperatures. 2. Lower response time for DRAM temp sensor from 60s to 5s. 3. Increase throttle priority to the charger when DRAM hit passive temperature from 100 to 200. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26cheza: Wrap FMAP sections with calibration data in RO_PRESERVE sectionJulius Werner
The Cheza board contains a couple of non-standard FMAP sections that contain per-board calibration data. When flashing new firmware to the board, care should be taken to copy these sections over so that all features can still function correctly afterwards. This patch wraps a new RO_PRESERVE FMAP section around these sections to make them easier to preserve as a group. Change-Id: I77919336f609a1be399598736f46921c3da99e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settingsMichał Żygowski
Configuration of pins exposed by superIO are inconsistent between board variants. Each platform should have UARTs enabled, this is expected behaviour of these pins. Given that APU2_PINMUX_UART_x can be set for all boards as default. Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26mb/lowrisc: Remove the Nexys4DDR portJonathan Neuschäfer
This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Remove TPM1 optionMichał Żygowski
Apu2 boards use Infineon SLB9665 TT 2.0 module which is TPM2.0. Remove TPM1 option to allow choice between TPM1 and TPM2. SLB9665 TT 2.0 detection fixed in change 21983. Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz)peichao.wang
Need to tune I2C bus 6 clock frequency under the 400KHz Bug=b:116543001 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 399.1KHz Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"Seunghwan Kim
This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: Use values from driver instead of hardcoding in firmware (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28690 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for PhaserPeichao Wang
Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectively. BUG=none TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28669 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-25mainboard/google/kahlee: Only read a single vendor from oem.binMartin Roth
Since each variant has a separate build, we don't need to support multiple manufacturers in a single file. BUG=b:79874904 TEST=Build, boot, see updated mainboard manufacturer Change-Id: I0ccf207ba8d5e5200aa4b19c46784bbda82f7b6e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-09-25mb/google/kahlee/variants/liara: Disable NbP-state on LiaraAmanda Huang
To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb/asrock/g41m_vs3_r2: Add mainboardArthur Heymans
The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/octopus: Create ampton variantJustin TerAvest
This commit creates an ampton variant for Octopus. The initial settings are copied from Bip, but the following changes are made to support hardware differences: * GPIO_66 is not connected (LTE). * GPIO_67 is not connected (LTE). * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet. * GPIO_143 is not connected. * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected. * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146. * GPIO_213 is not connected. * GPIO_214 is not connected. BUG=b:111498206 TEST=None Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/28663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-21mb/intel/coffeelake_rvp: Add whiskey lake rvpLijian Zhao
Add new mainboard variant of whiskey lake rvp, which is primary validation platform for whiskey lake silicon, support socket DDR4 memory module. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/google/poppy/variants/rammus: Disable command TriState for rammusmarxwang
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL. BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28568 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/intel/coffeelake_rvp: Correct LPDDR4 to DDR4 in mainboard infoLijian Zhao
There's only DDR4 or LPDDR3 support for coffelake processor line, details can be found out on EDS #570805. BUG=N/A TEST=N/A Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/intel/coffeelake_rvp: GPIO support for whiskey boardLijian Zhao
Add gpio programming difference for whiskeylake rvp platform. BUG=N/A TEST=N/A Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28367 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21google/kukui: Set up EC_IN_RW GPIO for ChromeOSTristan Shieh
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch, depthcharge will fail to tell if the EC firmware is RW. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC_IN_RW GPIO. Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variant/nocturne: set DMIC1 to NCNick Vaccaro
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28689 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mainboard/google/kahlee: allow oem.bin file to update smbiosMartin Roth
Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, boot, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-21mb/google/octopus/variants/fleex: Update DPTF parametersSumeet Pawnikar
Update Power Limit1 and Power Limit2 values along with stepsize. Correct the charger effect for Temperature sensor2. BUG=b:112448519 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/lenovo/{T500, R400, W500}: Unify variants under T400Arthur Heymans
A negative side-effect is that those boards disappear from the board-status output, but this is an issue on all variants. Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/zoombini: Use Chrome EC BOARDID definitionKarthikeyan Ramasubramanian
The board_id() definition is the duplicate of chrome EC board_id definition. Remove the duplicate definition and select EC_GOOGLE_CHROMEEC_BOARDID Kconfig item. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/28609 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-20mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
Update DPTF settings based on recommendation from thermal team. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28666 Reviewed-by: Todd Broch <tbroch@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meepWisley Chen
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT. BUG=b:115965629 TEST=verified it in meep proto board which rework ram id. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 Reviewed-on: https://review.coreboot.org/28658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-20mb/lenovo: Add libgfxinit support on Lenovo T520Evgeny Zinoviev
Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-18mb/asrock/g41c-gs: Link separate gpio.c filesArthur Heymans
With the addition of new boards using macros to set per board settings in the same gpio.c file is getting too complicated so link separate files. Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-18mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM valuesRichard Spiegel
AMD has tested careena, and for the time being is recommending a scalar of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM configuration code, set the desired values. BUG=b:111561217 TEST=none, code was tested with grunt. Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18mainboard/google/kahlee: Set EMMC reset pin to output lowMartin Roth
While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/google/kahlee: Don't set global subsystem IDsMartin Roth
These values override the default subsystem IDs, and aren't needed. BUG=b:113253260 TEST=Boot grunt Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/pcengines: select ADD_SEABIOS_SERCON_PORT_FILEMichał Żygowski
PC Engines boards are interfaced mainly via serial console. Enable SeaBIOS serial console for these boards by default when SeaBIOS selected as payload. Change-Id: I9e65dd1e28859028c8c46f28a5442de8c59d4893 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27824 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-17mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/buddy: Add board as variant of google/auronMatt DeVillier
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron, with the following changes: - add buddy-specific variant code - add handling to auron for buddy's lan init, which no other variants have - add handling to auron's mainboard ACPI due buddy having different PCIe port assigments than all other variants Ported from Chromium branch firmware-buddy-6301.202.B, commit ebb82ce [Buddy: Lock management engine + SPI descriptor] Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/auron: Clean up variant-specific romstage codeMatt DeVillier
Use an empty weak function for variant_romstage_entry(), rather than having separate empty functions for boards which don't utilize it. Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-16google/kukui: Configure EMMCTristan Shieh
Set up EMMC gpios for payloads. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-16mb/google/poppy/variants/rammus: fix S0ix entering issueZhuohao Lee
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and CIO2 devices to avoid the system failed to enter S0ix. BUG=b:114502527 BRANCH=master TEST=On DUT, echo freeze > /sys/power/state 1. check the S0ix status on EC console 2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-16google/kukui: Notify EC that AP is in S0Hung-Te Lin
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side, pad R23) that is supposed to be high in S0, and low in S3 (and X/don't care in S5). This should be set as early as possible in bootblock. BUG=b:113367227 TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high. BRANCH=None Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-16mb/intel/coffelake_rvp: Implement mainboard memory informationLijian Zhao
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform for easier collabration on newer platform. The setting in memory.c get from board design itself. BUG=N/A TEST=Build and boot up with whiskey lake rvp platform. Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28257 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16mb/google/poppy: Set UPD CmdTriStateDis for AtlasCaveh Jalali
This patch sets the MRC UPD CmdTriStateDis for the atlas boards. Atlas is a LPDDR3 design without RTT for CMD/CTRL. The original change for nocturne is I0f593761dcbd121e7e758421af178931b9d78295 mb/google/poppy: Set UPD CmdTriStateDis for Nocturne BUG=b:111812662 Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-15mb/lenovo: Add Lenovo W500 as clone of Lenovo T400Paul Menzel
At ECC 2017 user Bob reports, that an image built for the Lenovo T500 runs on the Lenovo W500 without any issues. Change-Id: I17fd9725ab85ba2f0c99a70f40e35432265a81c1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22226 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug
Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15soc/sifive: move ram_resource to mainboardPhilipp Hug
ram_resource is board specific and should be moved there. Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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