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2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09superio/serverengines/pilot: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09Squelch some warnings from KconfigKyösti Mälkki
Overriding global config entries in mainboard directory Kconfig files often raise unnecessary warnings. Squelch some of those. Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5699 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09rambi: Enable DPTFDuncan Laurie
This enables the DPTF framework, but it doesn't do much without some sort of kernel+user components to drive it. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179480 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5003 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09rambi: Set panel power timingsDuncan Laurie
These are the values that are seen with VBIOS and may need tweaked for derivative panels. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179365 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5001 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: change SD card pulls to 20KAaron Durbin
Now that the SD card controller is limited to the SD card 2.0 spec it's possible to use 20K pulls for the pads. BUG=chrome-os-partner:24423 BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without any errors. Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179423 Reviewed-on: http://review.coreboot.org/4999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: limit SD card controller to 2.0 specAaron Durbin
The rambi board can only meet the SD card 2.0 specification. Therefore, the controller capabilities need to be overridden to match. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows high speed as maximum timing as well as 3.3V signal voltage. Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179415 Reviewed-on: http://review.coreboot.org/4998 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09rambi: export SPI write-protect GPIO correctlyAaron Durbin
Bay Trail has 3 banks of gpios. Therefore, in order to properly identify a gpio the specific bank number as well as the GPIO within that bank is needed. The SPI write-protect GPIO is GPIO 6 within the SUS bank (offset 0x2000). BUG=chrome-os-partner:24324 BUG=chrome-os-partner:24408 BRANCH=None TEST=Built and booted. Looked at GPIO sysfs in the chromeos_acpi directory. Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179195 Reviewed-on: http://review.coreboot.org/4995 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08ChromeOS boards: Always build code for bootmode strapsKyösti Mälkki
Leave it under BOOTMODE_STRAPS to control whether these have any functional meaning on the build. Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08ChromeOS boards: Fix includesKyösti Mälkki
Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08Declare get_write_protect_state() without ChromeOSKyösti Mälkki
Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08Rename from save_chromeos_gpios() to init_bootmode_straps()Kyösti Mälkki
This feature is no longer specific to ChromeOS builds. Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08ChromeOS boards: Use explicit include of chromeos.cKyösti Mälkki
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08superio/fintek/f71869ad: Make hwm devicetree configurableEdward O'Callaghan
Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5580 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08superio/fintek/f71869ad: Configure multi-func reg in devicetreeEdward O'Callaghan
Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08mainboard/jetway/nf81-t56n-lf: Improve diags in romstageEdward O'Callaghan
romstage reports a completely unintelligible printf of "error level:", fix this and document meaning of the return values in source. Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5465 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08rambi: Make ec_in_rw a legacy GPIOShawn Nematbakhsh
ec_in_rw needs to be read by depthcharge, which only supports legacy GPIOs. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge detects the proper ec_in_ro state. BRANCH=None Change-Id: I25802b445c795eb85580c22d880efee8eeb21318 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4993 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-05-08rambi: Change eMMC pin PUs to 2KShawn Nematbakhsh
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up on certain boards. BUG=chrome-os-partner:24353 TEST=Manual. Burn FW on board that previously failed to boot eMMC, verify chromeos can now install + boot from eMMC. BRANCH=none Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4991 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: configure SD card signalsAaron Durbin
Rambi 1.5 boards use the native SD card controller on baytrail. Therefore, enable those signals. The CLK, D*, and CMD pins use 2K pulls as these were shown to not exhibit any errors when doing reads or writes to a DDR50 sd card. Note that if a servo is connected on needs to enable the sd_vref_sel rail to pp1800 as this causes issues with card detect if it is not set to pp1800. BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Tested sd card read and write works in kernel. Also noted that write protect detection works as well. Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178961 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4990 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: configure the LPE audio codec clockAaron Durbin
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0]. Configure it for 25MHz. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Noted message in console output. Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178781 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4987 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-07rambi: Remove outdated commentPatrick Georgi
Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5691 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07rambi: handle single channel configsAaron Durbin
Some 1.5 boards have a single channel ram configuration. Accomodate such configs. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built and booted ChromeOS. Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178340 Reviewed-by: Nick Sanders <nsanders@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: http://review.coreboot.org/4983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: use SERIRQ pad as keyboard irq in gpio modeAaron Durbin
The level shifting between 3.3V and 1.8V for the SERIRQ signal is not working. Instead use the SERIRQ pad as a gpio which is used as a direct IRQ signal for the keyboard interupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi. Keyboard works with associated EC change. CQ-DEPEND=CL:177189 Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177223 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4979 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: make ramids non-legacy gpio inputsAaron Durbin
The romstage code for rambi uses the mmio way of reading inputs. However, this is a problem is the GPIOs are set up as legacy mode. Subsequent warm resets mean the ram_id is read incorrectly. Ensure the ram_id is read consistently by keeping the GPIOs for ram_id in mmio mode. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted. And rebooted. Now seeing consistent ram_id values on warm resets. Change-Id: Ieff98c000be80998854f325754f1e819975d2be5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177230 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: distribute IRQs away from PIRQA on pci devicesAaron Durbin
Some of the drivers in the kernel were not so happy about having shared IRQs. Also, sharing IRQs means more code needs to be run in interrupt context to determine if the IRQ was meant for a particular device. Fix this. No more 'mmc1: got irq while runtime suspended' messages. BUG=chrome-os-partner:24056 BRANCH=None TEST=Built and booted. Looked at /proc/interrupts and noted no more sharing between pci devices. Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176792 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4973 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: fixup settings so trackpad can be found in kernelAaron Durbin
The kernel chromeos_laptop driver nomenclature expects the board name to not be in all caps. Fix this as well as the i2c address for the trackpad. BUG=chrome-os-partner:24307 BRANCH=None TEST=Built and booted. trackpad device is found. IRQs still not working yet. Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176680 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: Add DIRQs for trackpad and touchscreenShawn Nematbakhsh
Also add the relevant info about these pins to the ASL tables + add SMBIOS type 41 data for these parts. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8 Reviewed-on: https://chromium-review.googlesource.com/176299 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-06rambi: disable HDA deviceAaron Durbin
For some reason HDA can now be disabled. It's unclear what changes in the baytrail code allowed this to happen, sadly. BUG=chrome-os-partner:22871 BRANCH=None TEST=Noted hda is not in lspci. Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176394 Reviewed-on: http://review.coreboot.org/4961 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: enable SCI and SMI gpiosAaron Durbin
Rambi has 3 pins that need to be configured for SCI and SMI: 1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC. Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted. BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works. Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176393 Reviewed-on: http://review.coreboot.org/4960 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mainboard EC - SCI and SMI fixesAaron Durbin
As rambi is a baytrail board it doesn't have a dedicated wake pin. Therefore, one needs to enable the proper GPIO to wake up the sytem before going into S3. BUG=chrome-os-partner:23505 BRANCH=None TEST=Put system into S3. Keyboard press created wake event. Also, typed 'lidclose' on EC console while at recovery screen. Machine properly shutdown. Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176392 Reviewed-on: http://review.coreboot.org/4959 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: include the EC devices normally on superioAaron Durbin
The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: update EC supportAaron Durbin
Fix the SMI and SCI gpios for Rambi. Also, add in the EC callbacks for the SMI handler. Note that the handler for GPI SMIs has not been tested yet as baytrail chipset code doesn't yet support setting up those configurations yet. BUG=chrome-os-partner:23505 BRANCH=None TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts for the EC's SCI GPI. Also was able to see Chrome EC messages with CONFIG_DEBUG_SMI and powering down at the dev screen. Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176077 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4948 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06baytrail: configure acpi SCI irqAaron Durbin
Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4946 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mirror bayleybay's eMMC gpio setupAaron Durbin
These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: Fix eDP panel functionalityDuncan Laurie
For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4944 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM StringTrevor Mosey
linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC version string before loading, this code copies the vendor BIOS by exposing this string. This was originally part of x60's mainboard.c Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845 Signed-off-by: Trevor Mosey <uberushaximus@gmail.com> Reviewed-on: http://review.coreboot.org/5638 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05baytrail: fix up FADTAaron Durbin
The FADT for baytrail had incorrect offsets leading to the kernel spewing a huge mess of ACPI errors. Fix these offsets to be initialized in the chipset code. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted into kernel on rambi. Login screen comes up. Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175663 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4941 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05baytrail: interrupt routing supportAaron Durbin
This provides the initial support for interrupt routing in bay trail. It includes both acpi changes and board changes to ensure the interdependencies are met with the current ASL code. The PIRQ routing is handled by the mainboard exporting an irqroute.h header that describes the per device and PIRQ PCI settings. There are still a lot of ACPI errors in the kernel with this change, though. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted rambi into kernel. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e Reviewed-on: https://chromium-review.googlesource.com/175700 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Fix BiosCallouts table formattingKyösti Mälkki
Already done for fam15tn and fam16kb. Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Use common calloutsKyösti Mälkki
Backported from fam15tn and fam16kb. This also implements GetHeapBase() to satisfy some requirements of HAVE_ACPI_RESUME for the following boards: amd/inagua amd/south_station amd/union_station asrock/e350m1 Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5658 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Add fam14_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5657 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05jetway/nf81-t56n-lf: Revert change on function prototypesKyösti Mälkki
These function prototypes to remain identical across all AGESA families. Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add GetHeapBase()Kyösti Mälkki
While fam15 boards do not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add GetHeapBase()Kyösti Mälkki
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam16kb: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Use common calloutsKyösti Mälkki
Backport from fam15tn and fam16kb. Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add fam15_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 11:15:58 +0000