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2020-01-11src/mainboard/*.asl: Remove _HID / _ADR objects overlappingJonas Moehle
ACPI spec: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Signed-off-by: Jonas Moehle <ad-min@mailbox.org> Change-Id: I949393558f5af66689c167b2e593a1461f641962 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37935 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10HP sandy/ivy laptops: Sort Kconfig `select` linesAngel Pons
Sort them alphabetically. Change-Id: Ica7462d28d2aad184b6545db46547a01bc2a8ccb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/revolve_810_g1: Drop default DRAM_RESET_GATE_GPIOAngel Pons
When this board was added, S3 resume was tested and working, so it must be good enough. Change-Id: Ie095868ea2de7846b995271baf8155e57b495e40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/8770w/Kconfig: Drop INTEL_INT15Angel Pons
This laptop does not have integrated graphics. Change-Id: Id2209973f66536c8a3ead4bc3e9d5a05b7970c64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/{folio_9470m,revolve_810_g1}: Trim gfx.did to sizeAngel Pons
These values are the same that were hardcoded in autoport before. As done in commit 08caa79 (util/autoport: Trim gfx.did to size), ensure that the hardcoded values make at least some sense. Change-Id: I9950fd10e45f5016611a5d5b6a9e41c2b0f25a5f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38086 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10HP sandy/ivy laptops: Enable SMBus on devicetreeAngel Pons
It has no reason to be disabled. Change-Id: Iba82b6f71bc3d3a86576b719f2709595b530b702 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10HP sandy/ivy laptops: Align devicetreesAngel Pons
This makes it easier to spot differences. Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10HP sandy/ivy desktops: Fix Kconfig symbol namesAngel Pons
hp/z220_sff_workstation was using BOARD_HP_COMPAQ_8200_ELITE_SFF_PC, and hp/compaq_8200_elite was using a very long name. Fix that. Change-Id: I434cde42c7b9f30f8de77b96bc924aa298bad921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/*/devicetree.cb: Move northbridge devices upAngel Pons
It makes more sense for them to be above the southbridge block. Change-Id: I7dc06a46123f4bfc23d91f9c8cc4c9bdc4fb64f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DTRT CPU Throttle Effect on TSR0 change to TSR3. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38299 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" modeMike Banon
Set up the proper IRQ routing for OHCI/EHCI devices which appear if XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set). Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode. They also work fine if XHCI controller is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-10mb/lenovo/t431s/devicetree: Rebalance against t430s onePeter Lemenkov
Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37600 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/t431s/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37301 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10src: Remove blank acpi_tables source filesKarthikeyan Ramasubramanian
Due to build rules, dummy acpi_tables source files were added in many mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3 ("src/arch/x86: Build mainboard acpi_tables source if present"), the build system will build mainboard acpi_tables only if present. Remove the dummy/empty/blank acpi_tables source files. BUG=None TEST=Build test with some google mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-10mb/hp/*/devicetree.cb: Inherit the subsystemidAngel Pons
Since all the `subsystemid` lines in these devicetrees use the same values, factor them out via inheritance. There are some exceptions though. There are some enabled devices which lack a `subsystemid` entry. Looks like HP uses the same subsystem ID on every device, so assume that these devices should also use that subsystem ID as well. While we are at it, tidy up all the now-empty device blocks. Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38081 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2Michał Żygowski
Enable COM2 port on SuperIO if UART index is 1. This change allows to use full RS232 COM1 port for different purposes when COM2 is selected as main port. TEST=flash coreboot with console on COM2 and observer output with UBS-TTL converter connected to COM2 header on PC Engines apu1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-10mb/facebook/monolith: Remove SDIO controller from devicetreeWim Vervoorn
The SDIO device is disabled so remove it from the devicetree. BUG=N/A TEST=build Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/facebook/monolith: Enable HDA for HDMI outputWim Vervoorn
The HDA controller was disabled because no codec exists on the board. However, this also disabled audio over HDMI. To correct this, enable Azalia and the HDA controller in the devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd fileWim Vervoorn
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is expected by some parts of the code. Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region. BUG=N/A TEST=tested on facebook monolith Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/**/devicetree.cb: Remove untrue commentsAngel Pons
Even if they were corrected, they just rephrase the code. Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/lenovo/t530/devicetree: Use subsystemid inheritancePeter Lemenkov
Missing PCI IDs are checked against those collected at https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad. Change-Id: I61457b7a791dc3341d582f67e651acc6230c525c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37399 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Rebalance against x220 onePeter Lemenkov
Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37603 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37384 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1_1st_gen/devicetree: Use subsystemid inheritancePeter Lemenkov
PCI ID was changed according to the reports from Linux Hardware Project: https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad Change-Id: I67b81a4c9378c13d557e5d9c5d3797cebeeff5a1 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/google/fizz: Add Endeavour variantJeff Chase
Use the existing Karma variant as a base. BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/msi/ms7707/devicetree.cb: Align contentsAngel Pons
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/wtm2/devicetree.cb: Align commentsAngel Pons
Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/emeraldlake2/devicetree.cb: Align contentsAngel Pons
Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/dg43gt: Make devicetree prettierAngel Pons
Use lowercase for hex constants and align comments and register values. Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/intel/dcp847ske: Make devicetree prettierAngel Pons
Align contents and fix some redundant comments. Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/foxconn/d41s/devicetree.cb: Indent with tabsAngel Pons
As on most other boards, use tabs to indent the devicetree. Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/compulab/intense_pc: Reformat devicetreeAngel Pons
Use subsystemid inheritance, which results in a much more compact devicetree. In addition, align and correct various comments. Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/compulab/intense_pc: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Iaa557b18c34584dccb5c889ab8bd2173ed4ea04b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/roda/rk886ex/devicetree.cb: Align commentsAngel Pons
Change-Id: I67e3149657c04f72aac0b20bc31af338129a13b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5ql-em/devicetree.cb: Do minor fixesAngel Pons
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8z77-m_pro: Make devicetree prettierAngel Pons
Align comments, and make PCIe port comments consistent. Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode. Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants and align some comments. Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants, inline a lone `end` and align a comment. Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro: Make devicetree prettierAngel Pons
Replace a bunch of spaces with tabs, put host bridge and friends above southbridge, fix "TPM Module" (Trusted Platform Module Module) and add some empty lines to help the reader. Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/veyron/devicetree.cb: Drop illogical commentAngel Pons
This comment seems to have been copied off some QEMU board. As it would not apply to any veyron variant, drop it. Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/nyan/devicetree.cb: Correct some commentsAngel Pons
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few minor typos. Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-09src/mainboard: remove MMIO macrosIdwer Vollering
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09AGESA,binaryPI boards: Declare some IRQ tables staticKyösti Mälkki
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B optionAaron Durbin
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer being used in the code. There's a runtime check for supporting fast read dual output mode of the spi flash. Remove the references to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B. Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08mb/google/hatch: Remove fixed IccMax valuesJamie Chen
Remove fixed IccMax values for all domains. IccMax will be selected by CPU SKU in fill_vr_domain_config function. BUG=b:145094963 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-05 19:25:44 +0000