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2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-26mb/google/poppy/variants/soraka: Configure unused pins as NCFurquan Shaikh
This change configures unused pins as not connected. Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/google/poppy/variants/nautilus: Update camera power enable GPIOsFurquan Shaikh
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mainboard/google/zoombini/variant/meowth: add PCH_WP_ODNick Vaccaro
Configure GPP_H12 as an input for PCH_WP_OD. BUG=b:72202352 BRANCH=none TEST=none Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Add Grunt touchscreen supportJustin TerAvest
This commit adds support for an Elan touchscreen device connected over I2C via devicetree. BUG=b:72121803 TEST=Confirm the device is probed for. Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Add Grunt devicetree i2c bus cfgJustin TerAvest
I2C bus configuration is generally set up in devicetree.cb. This change establishes listings for the buses so that they can be used (though followup changes should update the buses to have correct timings). BUG=b:72121803 Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Select DRIVERS_I2C_GENERICJustin TerAvest
This is required to add support for I2C devices on Kahlee to ACPI tables via devicetree.cb. Without this, operations are not emitted for I2C devices and the proper ACPI table entries are not generated. BUG=b:72121803 Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Correct grunt HWID in GBBJustin TerAvest
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296 comes from the lower four numbers from running: $ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST')) BUG=b:72436450 Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mb/intel/glkrvp: Select SOC_ESPI to enable eSPIShaunak Saha
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC and enable eSPI instead. TEST=Boot to OS Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-25mainboard/google/zoombini: add ACPI entry for cr50Caveh Jalali
This adds coreboot device tree entries on zoombini & meowth for the cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This is based on what we do for fizz. BUG=b:71722449 TEST=booted to linux on meowth: tpm_version command now sees the cr50. localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 localhost ~ # uname -a Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux localhost ~ # and we see interrupts when talking to the cr50: localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru pts 84: 4687 IO-APIC 84-edge cr50_spi TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 84: 4799 IO-APIC 84-edge cr50_spi localhost ~ # Change-Id: I9d503334502503ef49515e4a8736d967bc454a98 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24mainboard/intel/cannonlake_rvp: remove redundant settingLijian Zhao
Clean up the extra DRIVERS_I2C_GENERIC BUG=None TEST=None Change-Id: Ida32b6f99c40c022aa8548f7353abf1d60ba4ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24amd/torpedo cimx/sb900: Fix include directoryKyösti Mälkki
Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24mb/google/fizz: Add AC/DC loadline settingsGaggery Tsai
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mainboard/glkrvp: Ignore DMIC_DATA pin IOSSTATERavi Sarawadi
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice. By doing this, SoC can see the DMIC DATA and use for WoV processing. Thus configuring GPIO_173 as IGNORE IOSSTATE. TEST=put DUT in S0ix, verify DUT wakes up Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23246 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/google/fizz: Tune audio i2c parametersShelley Chen
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23grunt: Enable TPMChris Ching
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create the appropriate selection based on selected board, and if grunt then define the I2C address. BUG=b:69416132 BRANCH=none TEST=make all Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22960 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mb/google/reef,sand: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23google/kahlee/BiosCallOuts.c: Remove platform_FchParams_resetRichard Spiegel
Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[]. Finally, make platform_FchParams_reset() an empty function. BUG=b:64140392 TEST=Build gardenia. Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[] and get_gpio_table(). Then remove the get_gpio_table() call from BiosCallOuts.c. Finally, remove get_gpio_table() from google/kahlee/variants/baseboard/include/baseboard/variants.h. BUG=b:64140392 TEST=Build grunt. Build and boot kahlee, recording serial output. Search for "stage bootblock" and "stage ramstage", indicating GPIO being programmed. Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23soc/amd/stoneyridge/southbridge.c: Create a GPIO programming functionRichard Spiegel
Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23mb/google/poppy/variants/nami: Remove iccmax setting from devicetreeFurquan Shaikh
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings) provides correct iccmax settings for kbl-u based on the SKU. Thus, there is no need to override these values in devicetree. This change gets rid of iccmax settings in the nami devicetree. Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya
Add NHLT and dt support for max98373 amp BUG=None TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5 Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219Lijian Zhao
Add NHLT and dt support for Audio with Max98357 and DA7219 TEST=verified NHLT tables and SSDT entries BUG=None Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mainboard/google/zoombini: mrc cacheCaveh Jalali
this enables the MRC recovery cache for zoombini & variants. the Kconfig options are: HAS_RECOVERY_MRC_CACHE MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN one note of caution: early board builds will likely fail to boot with: tlcl_extend: response is 0 tlcl_extend: response is 0 tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 28b Failed to lock rec hash space(1f) Saving nvdata hard_reset() called! the fix is to boot into recovery once, then it's business as usual. using servo, this can be done with: dut-control power_state:rec BUG=b:71785303 BRANCH=chromeos-2016.05 TEST=boots on meowth... Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23298 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mainboard/google/zoombini: add EC to ACPI tablesCaveh Jalali
this adds missing ACPI entries for the EC, CPU, and power button. also, the EC to AP wakeup pin assignment is fixed. BUG=b:71819257 BRANCH=chromeos-2016.05 TEST=booted on meowth. /sys/class/power_supply now gets populated. Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/23237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-01-22mb/google/fizz: Remove IccMax settings from DTGaggery Tsai
This patch removes IccMax settings from device tree since they are handled in SoC code from patch e1a75d. BUG=b:71369428 BRANCH=None TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure the IccMax settings passed to FSP are from SoC code. Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: enable PCH_FP_PWR_ENVincent Palatin
Turn on the load switch to the FP MCU at startup, so the kernel can detect it and use it. The load switch enable pin is connected to the GPP_A11 PCH pin (aka PCH_FP_PWR_EN). BRANCH=none BUG=b:71986991 TEST=on Meowth, see the kernel detecting a cros_fp device at startup: [ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected. [ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: configure FP MCU SPI deviceVincent Palatin
Configure the FP MCU interface on GSPI1. BRANCH=none BUG=b:71986991 TEST=boot on reworked Meowth with a ZerbleBarn board attached to GSPI1 and see the cros_ec kernel driver detecting it. Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/asus/am1i-a: remove unwanted variableGergely Kiss
The variable t32 was originally used to do bitwise operations, but it is not required anymore. Also, it was assigned twice accidentally, which introduced a new Coverity Scan defect. Found-by: Coverity (CID 1385126: (UNUSED_VALUE)) Change-Id: I77afd5064304a36991f63cf1328e13820144efb6 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-18Intel i440bx boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Mainboards: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/azza/pt-6ibd src/mainboard/biostar/m6tba src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga-6bxe src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6156 src/mainboard/nokia/ip530 src/mainboard/soyo/sy-6ba-plus-iii src/mainboard/tyan/s1846 Change-Id: Id895963f9641bcaaa65e8a8cb21213a758a9ad80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23301 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18Intel i82810 boards & chips: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i82810 Mainboards: src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/ecs/p6iwp-fe src/mainboard/hp/e_vectra_p2706t src/mainboard/intel/d810e2cb src/mainboard/mitac/6513wu src/mainboard/msi/ms6178 src/mainboard/nec/powermate2000 Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23300 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18mainboard/google/zoombini/variant/meowth: add memory optionsNick Vaccaro
Add support for new memory stuffing options that will appear on the P1 meowth boards. new strap setting - associated SPD file ---------------------------------------- 0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex 0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex 0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17google/fizz: Fix barrel jack values for U42 and U22Shelley Chen
Our current U22 skus (celeron and i3) actually don't support PL2, but making sure that if we do decide in the future to use it to make sure PL2 and PsysPl2 values are set appropriately. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42 and 65W with barrel jack for U22. Change-Id: I084d0320128a6e05948023520a30c497c41be23b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17lenovo/z61t: Update for PNOT changeMarshall Dawson
Change the directory of the included cpu.asl file. This board seems to have been omitted in 0a4e0fd "Fix the PNOT ACPI method". Change-Id: Idc00197b1544006299e720dca59e02f6bf8f683c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23308 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-01-17mb/google/poppy: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17mb/google/nautilus: Add MIPI camera asl files for IMX258 and DW9807Andy Yeh
* Add IMX258 sensor entity * Add DW9807 VCM control entity * Enable CIO2 and IMGu in devicetree.cb TEST: Verified the MIPI camera function on DUT board Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Move PMIC specific objects to appropriate scopeRizwan Qureshi
Right now the poppy baseboard camera topology allows to add maximum of 2 sensors. The sensors can be of different vendors. The current ASL code structure doesn't allow sensor customization. Moving PMIC specific objects from sensor objects to PMIC scope and having separate sensor ASL files will help in unbinding the PMIC and sensor objects and allow some customizations. BUG=None BRANCH=None TEST=Build and boot soraka, make sure both camera's are working fine and also verify that the generated DSDT looks fine. Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Split ports and endpoints config for CIO2Rizwan Qureshi
The variant boards can have a custom endpoints, splitting the ASL code aids customizing the endpoints as per the variant board setup. BUG=None BRANCH=None TEST=build boot soraka, verify that the cameras are working fine and generated DSDT tables are same as before. Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17AGESA f15 boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i5000 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i5000 Mainboards: mainboard/supermicro/x7db8 mainboard/asus/dsbf Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i855 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i855 Mainboards: mainboard/lanner/em8510 Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 16:07:33 +0000