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2019-01-29mb/intel/icelake_rvp/../icl_y: Enable SaGvSubrata Banik
This patch enables SaGv on Intel ICL-Y RVP board. TEST=Able to build and boot to Chrome OS. Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-28mb/asus/h61m-cs: Add ASUS H61M-CSdevmaster64
Working: - USB (Partially. Check "Not working") - PCIe - PCIe graphics - All SATA ports - Native memory init - On-board audio (back and front) - S3 (Sleep and wake) Not working: - Fan control - USB (If the keyboard has a USB Hub or if the keyboard is connected through 2 or more hubs then it doesn't initialize in time. A simple reboot allows the keyboard to be used in SeaBIOS and the bootloader) Untested: - PS/2 - On board graphics Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2 Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com> Reviewed-on: https://review.coreboot.org/c/30767 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28mb/google/octopus: Fix termination for unused dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequencySeunghwan Kim
ELAN touchpad supports up to 400KHz, so we need to limit its CLK frequency to 400HKz. BUG=b:123376618 BRANCH=octopus TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mb/lenovo/thinkcentre_a58: Extend mb nameArthur Heymans
While branded as thinkcentre a58 this board can also be found as "L-IG41M". Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-28mb/google/sarien: Using HID over I2C to enable Melf TouchScreenChris Zhou
Current Melfas touchscreen driver cannot unregister ifself when connecting without Melfas touchscreen or connecting with other devices. And Melfas touchscreen FW can use I2C and HID over I2C driver, so switch to using HID over I2C driver. BUG=b:122710830 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 Reviewed-on: https://review.coreboot.org/c/31062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-26mb/qemu-riscv: update to match current qemu versionPhilipp Hug
Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25mb/lenovo/x131e: remove PMH7James Ye
This board does not have PMH7. Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31065 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/denverton_ns: Enable ACPI using intelblockJulien Viard de Galbert
- Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25mb/google/octopus: Override emmc DLL values for AmptonKane Chen
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25mb/google/sarien: Force power on after cr50 updateDuncan Laurie
By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25mb/google/sarien: Increse BIOS region size to 28MBLijian Zhao
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25mb/google/kahlee/variants/aleena: Add support Synaptics touch padLucas Chen
Add support Synaptics touch pad for Aleena/Kasumi. BUG=b:122549449 BRANCH=master TEST= Check if synaptics touch pad working in ChromeOS. Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31064 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that ↵Jan Tatje
need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-25mb/{kontron,supermicro}: Use pcidev_on_root()Elyes HAOUAS
Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-24src/mb/asrock/../g41m-s3: Remove spurious devicesAngel Pons
This fixes errors regarding "PCI: Leftover static devices" Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24mb/*/*/devicetree.cb: Move the ioapic device under the LPC bridgeArthur Heymans
This fixes spurious lines "child IOAPIC: 02 not a PCI device" and IOAPIC as leftover device. Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24mb/google/sarien/variants: Set tcc offset valueSumeet Pawnikar
Set tcc offset value to 5 degree celsius for Sarien system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-24mb/google/sarien: Fix recovery mode detectionDuncan Laurie
In order to support the physical recovery GPIO on sarien it needs to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO number in the coreboot table appropriately so that depthcharge can correctly determine the GPIO number. The same is done for the write protect GPIO in this table. Additionally since we are reading a recovery request from H1 it needs to cache the result since H1 will only return true on the first request. All subsequent queries to H1 will not indicate recovery. Add a CAR global here to keep track of the state and only read it from H1 the first time. BUG=b:121380403 TEST=test_that DUT firmware_DevMode Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31043 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24mb/google/octopus/bobba: Add support to handle PEN_EJECT eventKarthikeyan Ramasubramanian
Enable gpio_keys driver for bobba and add required configuration in the device tree to handle the pen eject event. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mediatek/mt8183: Move some initialization into mt8183_early_initYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL adds a new function mt8183_early_init, which includes all initializations that should be done in early stages. All mainboards using MT8183 should manually call it in either bootblock or verstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-24mb/google/hatch: Enable support for WWANMaulik V Vaghela
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to enable USB 2 port 6 and USB3 port 5 which is already enabled in device tree related changes. BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mb/google/hatch: Enable PCIe WLAN and BTMaulik V Vaghela
Enable PCIe WLAN for hatch 1. Enable PCI port 14 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 3 for PCI port 14 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-24Kconfig: Remove symbol names for choicesNico Huber
These are completely throwing Kconfig off, resulting in duplicate entries. Change-Id: I401467da686d5011a456b661a10170492a919c81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24cpu/intel/model_406dx: Remove the notion of CPU socketsArthur Heymans
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31032 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24mb/ocp/wedge100s: Add SuperIO supportPatrick Rudolph
* Enable COM1, COM2, PMC1 and PMC2 TODO: Look at additional configuration and EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-23mb/google/sarien: Replace B0D4 with TCPUSumeet Pawnikar
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/*/*/devicetree.cb: Make sandybridge devicetree uniformArthur Heymans
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-23mb/intel/icelake_rvp: Enable dptf functionalitySumeet Pawnikar
Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/29686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23mb/intel/glkrvp: Fix termination for dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23google/kukui: Revise FMAP layout for larger CBFSHung-Te Lin
Kukui with vboot enabled will build with `detachable_ui`, which needs larger space in CBFS for more complicated assets. So we need to revise FMAP sections: - BOOTBLOCK (not really used) only needs <= 32K. - GBB can be much smaller since assets moved from GBB to CBFS. - FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can get larger continuous space. - COREBOOT(CBFS) should take all space left. Since FMAP and COREBOOT have changed location, the system will need to reflash EC (which contains the new bootblock) as well. BUG=b:123202015 TEST=Builds and boots on Kukui P1 Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23mb/google/poppy/variant/nami: disable unused usb2 portsRen Kuo
disable unused usb2 ports of bard and ekko skus BUG=120874946 TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30986 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/arcada: Add settings for noise mitgationCasper Chang
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-23mb/lenovo/x131e: add VBTJames Ye
VBT was extracted from VBIOS ROM. Tested with libgfxinit, booting SeaBIOS into Linux. Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/pineview: Use parallel MP initArthur Heymans
Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
Use parallel MP init code to initialize all AP's. Also remove guards around CPU code where all platforms now use parallel MP init. This also removes the code required on lapic init path for model_6fx, model_1017x and model_f4x as all platforms now use the parallel MP code. Tested on Intel DG41WV, shaves off about 90ms on a quad core. Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/i945: Use parallel MP initArthur Heymans
Use the parallel mp init path to initialize AP's. This should result in a moderate speedup. Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is 26ms faster compared to lapic_cpu_init. This removes the option to disable HT siblings. Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-23mediatek/mt8183: Add Micron 4GB LPDDR4X DDR supportHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-23mb/purism/librem_skl: add 13v3 variantMatt DeVillier
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged since boards were initially shipped with 13v2 firmware, and changing it now would cause flashrom to throw a board mismatch error. Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: add support for 13v4/15v4 boardsMatt DeVillier
Add support for Kabylake Librem 13v4/15v4 boards, reusing existing 13v2/15v3 variants since board design unchanged (only SoC). Adjust identification strings, add Kabylake VGA PCI ID. Change-Id: Ia795b9c7373ea2e2acd3bef309320b58e9e8449d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: adjust CBFS_SIZEMatt DeVillier
Adjust default CBFS_SIZE to match that used in configs for building Change-Id: Ibe1312560a923dcdefb8af52a721ab76c0b08a2e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/google/poppy/variants/nami: close the FP power in S5Ren Kuo
close the FP module power in power off (s5) BUG=122887366 BRANCH=Nami TEST= build test firmware and measure the fp power enable pin Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30910 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Vincent Wang <vwang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/hatch: Enable SD card support for hatchMaulik V Vaghela
Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=Verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Add BMC KCS to ACPITimothy Pearson
The BMC KCS interface must be advertised to the host OS in order for automatic load of the ipmi module to work. Expose the KCS interface via ACPI. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19822 Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Enable IPMI KCS accessTimothy Pearson
The on-board BMC contains a hardware KCS interface. Allow access to it over LPC. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac6 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"Daniel Kurtz
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selectionSubrata Banik
hatch shouldn't make use of internal ec.bin through IFD tool. Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-20mb/google/octopus/variants: Disable xHCI compliance mode for FleexAmanda Huang
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 23:29:57 +0000