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2018-08-13mb: Get rid of unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27869 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13google/bobba: Add Raydium touch screen supportPan Sheng-Liang
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13mb/intel/dg43gt: Enable the GBEArthur Heymans
This was blindly copied from logs created under vendor BIOS in non-descriptor mode which apparently set LAND in BUC. Change-Id: I94c917600421ee742ece7f6f71309da80261da28 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-13mb/google/poppy/variants/nocturne: remove icc_max overridesNick Vaccaro
Remove icc_max overrides to allow SoC code to set proper icc_max based on CPU SKU. BUG=b:78122599 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash to nocturne, boot to kernel and verify device doesn't hang after a few minutes. Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27996 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/nocturne: update PL2 based on CPU skuNick Vaccaro
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27997 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/atlas: Update PL2 based on CPU skuGaggery Tsai
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27765 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/octopus/variants/fleex: Set up DPTF tableJohn Su
Follow thermal table (b:112274477 comment#1) for first tunning. BUG=b:112274477 TEST=Match the result from DPTF UI. Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13mb/google/octopus: Enable SAR config for Intel 9560 moduleJohn Zhao
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:112288077 TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry. Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Do not configure IOStandby for WLAN_PE_RSTFurquan Shaikh
PERST signal is asserted/deasserted by ACPI routines during suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in failure to resume from suspend state with wake-over-WLAN. This change removes the IOStandby configuration for WLAN_PE_RST. BUG=b:112371978 Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Configure WiFi wake as NC when using CNViFurquan Shaikh
When CNVi is being used, external wake using GPIO_119 is not required. This change configures GPIO_119 as PAD_NC if CNVi is taken out of reset. BUG=b:112371978 Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Use correct chip for CNVi deviceFurquan Shaikh
This change uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows up in ACPI node 2. It is possible to pass any parameters from devicetree to wifi driver for SSDT generation. BUG=b:112371978 Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Dynamically disable CNVi/PCIe deviceFurquan Shaikh
This change checks to see if CNVi module is out of reset: 1. If yes, then PCIe device for WiFi is disabled. 2. If no, then CNVi device is disabled. BUG=b:112371978 Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-08-12mb/google/octopus: Disable unused I2C2 in devicetreeFurquan Shaikh
I2C2 is unused on all octopus variants. This change disables it in devicetree. BUG=b:112458032 Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28016 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1Furquan Shaikh
This change updates GPIO configuration for fleex boards with id >= 1 This follows the same model as phaser: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. d. Disable unused I2C devices in devicetree. BUG=b:112458032 TEST=No errors observed on boot-up on fleex. Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/asus/maximus_iv_gene-z: Add VBTTristan Corrick
The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 3603). Tested with Linux 4.9 and everything works as expected. Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/28050 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10mb/google/octopus: add support for new shared memory configAaron Durbin
Allow for shared dram configuration by introducing a new table that collapses the common settings after removing the part numbers. When employing this scheme the part number comes from CBI. BUG=b:112203105 TEST=Placed part number in cbi. Faked out memory sku id. And enabled DRAM part num always in cbi. Everything checked out. Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up CMOS filesAngel Pons
Options that were deemed unneceesary on other code reviews have been removed from the layout files. In addition, the checksummed range has been extended to cover sata_mode and gfx_uma_size. Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard codeAngel Pons
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards. Based on another mainboard's code review comments, this patch improves the code quality of these three similar boards. ga-h61m-s2pv is tested and confirmed to be working, but I cannot say the same regarding the other two mainboards as I do not have them. Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10google: Remove board 'rotor'Julius Werner
Rotor is dead, long live [PROJECT NAME REDACTED]! Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27964 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: add support for fetching DRAM part number from CBIAaron Durbin
Add 3 new Kconfig options: DRAM_PART_NUM_IN_CBI DRAM_PART_NUM_ALWAYS_IN_CBI DRAM_PART_IN_CBI_BOARD_ID_MIN These control whether to 1. attempt to use CBI at all 2. always use cbi and 3. conditionally use cbi based on board id. The intent is that the MIN variant would be used for the tranisition period then cut over to ALWAYS after full transition. Since multiple OEMs have different schedules these options are there to bridge the gap. yorp. bip, and octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case someone does the MIN values are 255 to always take the old path. BUG=b:112203105 TEST=Set correct part number on phaser during testing. Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09google/grunt: Override BayHub EMMC driving strengthKevin Chiu
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: remove disable_periodic_retraining optionsAaron Durbin
The Micron material that was broken has long since been fixed that required this option. glkrvp had these stale entries and were subsequently copied to octopus. Remove the need for this option. BUG=b:35581751 Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/poppy/variants/atlas: Do not override icc_maxCaveh Jalali
Skylake SoC code now sets the icc_max based on the CPU SKU, so we should not hard-code it in the device tree. BUG=b:110890675 BRANCH=None TEST=boots on atlas Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-08-08mainboard/google/kahlee: Set SYSTEM_TYPE_LAPTOPRaul E Rangel
This configures the ACPI FADT perferred power management profile to PM_MOBILE instead of PM_DESKTOP. I'm not sure what impact this actually has. I just noticed the other boards have it set. BUG=b:110971913 TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config Change-Id: Iea1b8359b80d167e69745358f543f025713294ba Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08mb/intel/cannonlake_rvp/devicetree: Remove spurious CPP directivesArthur Heymans
The devicetree is not run through a C pre-processor, so remove it. Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27927 Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-07mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power onSeunghwan Kim
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on, it may cause damage on the GPIO pad. To prevent, we would set this pad to GPO on romstage before EDP power on. Since we need to cover all systems in market, I put it into romstage instead of early_gpio_table. BUG=b:111860510 BRANCH=poppy TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07mb/google/poppy: Add variant callback for romstage GPIO configurationFurquan Shaikh
This change adds variant callback to get GPIO configuration table in romstage and configures these GPIOs before memory training is performed. BUG=b:111860510 BRANCH=poppy Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07mb/google/poppy/variants/nautilus: Add SKU info to SMBIOSFurquan Shaikh
This change provides implementation of smbios_mainboard_sku() to add proper "skuX" string to SMBIOS table 1. BUG=b:112163362 TEST=Verified "dmidecode -t 1" reports skuX correctly. Change-Id: I7e42d2c80d791ea7170d066d2eeaa0c6811eb9c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06mainboard/google/kahlee: Add PSPP override settingMarc Jones
Add default PSPP AGESA setting for Kahlee/Grunt mainboards. BUG=b:112020107 TEST= build test Change-Id: I8a8605402379de88a04f3a16553c308513fa1531 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06google/grunt: Move PSP_SELECTABLE_SMU_FW to socRichard Spiegel
Now that an updated bootloader with important fixes is available at coreboot repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27844 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mb/google/octopus/variants/baseboard: Update Power Limit1Sumeet Pawnikar
Update power limit1 value from 8W to 10W. There is an error in the energy calculation for current VR solution on GLK. Experiments show that when power limit1 set to 10W, gained performance improvement with SoC TDP reaches max (6W) power. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/octopus/variants/fleex: Enable Weida touchscreen deviceCrystal Lin
This change adds ACPI properties for WDT8752A device. BUG=b:111402335, b:111102092 BRANCH=master TEST=Verify touchscreen on fleex works with this change Change-Id: Id186d5b87343007ae7e631d5d27464ee27e5b27d Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add rammus devicetree.cbZhuohao Lee
Use the default value for Iccmax which is specified in vr_config.c. The AcLoadline and DcLoadline keep the poppy value. Besides, the USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT and the others on the daughterboard are set to USB2_PORT_LONG. Those setting need to be fine tuned later. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add gpio settingZhuohao Lee
The gpio setting is based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add memory configurationZhuohao Lee
Add memory configuration based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add audio, mic and codec configurationZhuohao Lee
Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: change build directory to rammusZhuohao Lee
Move the build board directory from poppy to rammus. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I3a9fc2bbfe7261661f0c5c073baff0ff1434d09f Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/kahlee: Disable SATA in all boardsRichard Spiegel
Kahlee based boards don't use SATA, so disable SATA on all boards to save power. BUG=b:112139043 TEST=Build and boot grunt, checked the absence of SATA PCI. Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-05southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by defaultAngel Pons
Since only a handful of boards have descriptor blobs in the tree, it makes no sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard. This patch flips the default value of said variable, rendering all current overrides unnecessary. The few boards which have an IFD in the blobs repo use `select HAVE_IFD_BIN` to enable adding the IFD by default. Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed alongside the latter, and has been added to the boards with a ME blob as `select HAVE_ME_BIN`. Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well. Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04mb/pcengines/apu2: turn LED 2 and LED 3 off in final stageMichał Żygowski
Due to vendor's requirements LED 2 and LED 3 should be turned off in late boot process. Add appropriate functions to read and write GPIO status. Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04mb/pcengines/apu2: change GPIO settingMichał Żygowski
Change GPIO setting to use IOMUX to refer to GPIO by IOMUX register as in BKDG for Family 16h Models 30h-3fh Processor Rev 3.06. Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-03mainboard: Add ASUS P8H61-M LXTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driverMatt DeVillier
These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03mb/google/poppy/variants/atlas: Apply correct AC/DC loadlinesGaggery Tsai
This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b:111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27788 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cheza: Deassert USB hub reset pinJulius Werner
This patch makes sure we deassert the USB hub reset pin so the hub will work with the next board revision that drops the external pull-up. (Actual USB support comes in a later patch.) Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27790 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02cheza: Add board ID, RAM code and SKU IDJulius Werner
This patch adds the required callbacks to read all strapping IDs on Cheza. Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02mb/lenovo/x1_carbon_gen1: add vbtAlexander Couzens
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware. Thanks to Igor Lee. Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-02mb/google/poppy/variants/nami: Tune Fan speedSumeet Pawnikar
Tuning of fan speed for different temperature values. Earlier while running few benchmarks, fan was always getting on and starting at higher speed. With this change fan will start with lower speed and slowly speed gets increased if temperature continue going high. Thermal team provided these data after fine tuning of fan speed. BUG=None. TEST=Verified on Nami running with different benchmarks and observed fan speed. Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 03:17:41 +0000