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2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04src/ec,mainboard: Move weak smbios_system_sku() override inwardsEdward O'Callaghan
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:150735116 BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04mainboard/google/dedede: Migrate onto SKU ID/fw_config helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. dedede uses the non-legacy SKU ID space. squash in, mainboard/google/dedede: Migrate onto get fw_config helper BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-04mainboard/google/octopus: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-03mb/asrock/h110m: Explain why some SATA ports are emptyMaxim Polyakov
Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03mb/google/drallion: Enable cbfs SAR valueEric Lai
Enable read SAR value from cbfs. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
2020-03-03treewide: Replace BOARD_EMULATION_QEMU_X86Angel Pons
It is equivalent to the CPU_QEMU_X86 symbol. Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-03mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86Angel Pons
Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards. Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-03mb/*/Kconfig: Factor out MAINBOARD_VENDORAngel Pons
Only some mainboard vendors have a prompt for this option. Let's be fair and give this ability to everyone. Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03mb/Kconfig: Align ROM size optionsAngel Pons
Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03LGA1155 mainboards: Remove gfx.did and gfx.ndidAngel Pons
They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-03mb/google/dedede: Add memory initialization support for dededeMeera Ravindranath
Update memory parameters based on memory type supported by dedede 1. Update dq/dqs mappings 2. Update spd data for Micron Memory 3. Add SPD data binary files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02mb/google/kohaku: Add LPDDR 16G 2133 supportSeunghwan Kim
BUG=b:149775711 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1. Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02mb/**/dsdt.asl: Remove "Some generic macros" comment, againAngel Pons
It provides no useful information, so it might as well vanish. This follows commit 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48. Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02nb/intel/sandybridge: Fix VBOOTPatrick Rudolph
The VBOOT code can be compiled but it asserts with: ASSERTION ERROR: file 'src/security/vboot/common.c', line 40 Start VBOOT in bootblock to fix the assertion. Tested on Lenovo X220: The assertion is gone, the platform boots again. Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02mb/google/octopus: support new Elan touch panel for FoobTommie
This is new elan touch screen IC, which includes touch panel and USI pen. BUG=b:149800883 BRANCH=octopus TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com> Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-03-02mb/google/hatch/var/jinlon: Disable EPS on some SKUsRajat Jain
Disable EPS on the SKUs that do not have it. Change-Id: I7305097beea3484634933ab856fd084933868a10 Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02mb/google/hatch/var/jinlon: Enable gfx/generic driverRajat Jain
Enable the GFX device for Jinlon. Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02mb/emulation/qemu-aarch64: Add ARM trusted firmware supportPatrick Rudolph
Linux expects a working PSCI and hangs if not found. Add BL31 into CBFS as '-M virt,secure=on -bios ' commands line arguments cause qemu's internal PSCI emulation to shutdown. BL31 is placed in qemu's SECURERAM memory region and won't conflict with resources in DRAM. Tested on qemu-system-aarch64: Fixes a hang and allows to boot into Linux 5.4.14 userspace. Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02mb/emulation/qemu-aarch64: Add MMU supportPatrick Rudolph
Enable MMU in bootblock. Makes qemu look more similar to real hardware. There's no real need to activate the MMU. Tested on qemu-system-aarch64: 5 page entries are used out of 32. Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02superio/nuvoton/npcd378: Switch to superio/commonPatrick Rudolph
Replace DSDT ACPI code and DSDT injection with a SSDT only solution. The current implementation shows some issues on current Linux, which might be due to external ACPI objects, which are then injected into DSDT or the fact that those objects only use 3 characters. Replace all the DSDT code with an SSDT generator. Tested on HP Z220: Boots into Linux with no ACPI errors. The SSDT can be disassembled. Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-28mainboard/google/volteer: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. volteer uses the non-legacy SKU ID space. BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28mainboard/google/hatch/puff: Toggle on TetonGlacierModeEdward O'Callaghan
Leverage in Puff to avoid diskswap variants. Later this could become part of the baseboard definition and hatch diskswap variants migrated over to use it as well. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28mainboard/google/hatch: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27mb/google/hatch/var/jinlon: Configure GPP_E0 as outputRajat Jain
Configure GPP_E0 as output for view angle management Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Signed-off-by: Rajat Jain <rajatja@google.com>. Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: configure ESPI IO decode range for chrome ECAamir Bohra
Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: Enable display supportAamir Bohra
1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. TEST=Verify display on EDP panel in OS Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mb/google/hatch: reflow commentPatrick Georgi
Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-26mb/intel/tglrvp: add Tiger Lake memory initialization supportSrinidhi N Kaushik
Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-26mainboard/hatch: Fix GPE wake commentsEdward O'Callaghan
The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down through the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-26mb/google/dedede: Update GPE configurationKarthikeyan Ramasubramanian
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is routed to GPP_C12 GPIO. Update the GPE configuration accordingly. BUG=None TEST=Build the mainboard. Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mb/google/dedede: Enable host bridge deviceAamir Bohra
Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-26mb/google/fizz: allow 8 bit sku idsJeff Chase
Change-Id: I663678a4c572fe80298f7388870d5cd403122b98 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-02-25mb/hp: Set CBFS_SIZEPatrick Rudolph
Overwrite the default of 1 MiB with the actual bios region size set in the stock IFD. Allows to use payloads like TianoCore without manually touching the CBFS_SIZE. Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39073 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2Michael Niewöhner
Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-25mb/supermicro/x11-lga1151-series: fix GPIO reset mappingMichael Niewöhner
When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset value of 0x0 is only defined for GPD pads. For any other GPIOs this maps to 0x3. On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". Set the right value (0x3<<30) for the affected GPIOs. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-25mb/amd/samba: Drop board leftoverElyes HAOUAS
lippert/hurricane-lx doesn't exist anymore (see Change-Id: I87e3963). Change-Id: I6d1c3a846c5bbb5fdc74178d0cf8a3cdaae1a010 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39076 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/inagua: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I55bf3004c728bb42ee51dfa917c58d97c56502cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38876 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Iad86755952204bb1a56ef341e626b0627a958467 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38870 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/union_station: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38875 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/38877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/south_station: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Iba1d020b9e565e3c6c89a97114084d72a00b2a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38871 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 11:55:00 +0000