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2021-05-21fix xfixed_eq820g2Iru Cai
2021-05-21820g2: update gpe,smiIru Cai
2021-05-21mb/hp: Add EliteBook 820 G2Iru Cai
It can now boot Arch Linux from SATA and USB. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
2021-05-21mb/google/mancomb: Enable S0ixKarthikeyan Ramasubramanian
BUG=b:188446049 TEST=Build and boot to OS in mancomb. Ensure that the system can suspend and resume successfully. Ensure that the sleep state GPIOs are reflecting the state as expected. Change-Id: I43e86a07075fe66f89c2c5665adc209e985e4f04 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-21mb/google/dedede/var/drawcia: Support HDMI VBT for DrawperTony Huang
Drawper support LTE+HDMI, so use DB_PORTS_1A_HDMI_LTE to select HDMI VBT output for it. BUG=b:186393848 BRANCH=dedede TEST=Build and boot to OS check HDMI output works. Change-Id: Ibf34cce1e3cbfce8a71dce880c50f85db9295b1e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-21mb/google/dedede: Add DB_PORTS FW_CONFIG in devicetreeTony Huang
DB_PORTS_1C_1A_LTE 6 DB_PORTS_1C 7 DB_PORTS_1A_HDMI_LTE 8 BUG=b:186393848 BRANCH=dedede TEST=build pass Change-Id: I8632960d7e538402bf033d07402116dac848f5ac Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-21mb/google/mancomb: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21mb/google/guybrush: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/puff/var/dooly: Add gpio_keys for mic mute switchBen Zhang
UI monitors this input event and sends global mic mute command to CRAS when the physical switch is toggled. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on DUT. Apply crrev.com/c/2870806 with chrome cmdline flag and verify global mute is triggered. Verify sequences of switch toggle and suspend/resume. Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3 Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/asus/p8z77-series: unselect MAINBOARD_HAS_TPM1 from p8z77-m_proBill XIE
MAINBOARD_HAS_TPM1 should not be selected, since the module is replaceable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ia3790154476b0db54f37e1f3abb91ba5ee891c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO remains identical when not adding the .config file in it. Change-Id: I7f1d93e500153a9821e7ddb693d77c864c879f0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-v_lx2: Extract overridetreeAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2 remains identical when not adding the .config file in it. Change-Id: Ia84b07f5fec3c2969134b0d0bc39248d50ac04ff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-series: Always select `INTEL_INT15`Angel Pons
The mainboard.c guard was only added to preserve reproducibility when unifying the boards. The `install_intel_vga_int15_handler` function does nothing when `VGA_ROM_RUN` is not selected. Remove the guard and always select `INTEL_INT15` for simplicity. Change-Id: If38ca49dba81921a3e7abe22542ae74d8914a38d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Transform into variantAngel Pons
To preserve reproducibility, temporarily guard mainboard.c contents. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO remains identical when not adding the .config file in it. Change-Id: I05e272690ca78f6b9e22b1db1c36cb9e5a7afe3c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Reorder `_PTS` and `_WAK`Angel Pons
Done to preserve reproducibility when switching to a variant setup. Change-Id: I4f3663d3b58c6245c9b73d370a48b8745ea5b95b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-v_lx2: Transform into variant setupAngel Pons
Get ready to squash all Asus Z77 boards together, so as to factor out some redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2 remains identical when not adding the .config file in it. Change-Id: I701ec4adbc65732ffc0a60d311bf07bf7f414ebf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8h61-m_lx: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54390 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/h61m-cs: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I34eb5387fddcb3505c9218b20b706b773e979b0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54389 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_pro: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: I443d3823e32a246a89ff12e52a0301b2c252e23b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54388 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_lx3_r2_0: Extract overridetreeAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetreeAngel Pons
Done to preserve reproducibility when switching to overridetrees. The H61 PCH only supports 6 PCIe root ports anyway. Change-Id: I926d62dda512e435d44c0646083c7722427dc80b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54386 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/h61-series: Always select `INTEL_INT15`Angel Pons
The mainboard.c guard was only added to preserve reproducibility when unifying the boards. The `install_intel_vga_int15_handler` function does nothing when `VGA_ROM_RUN` is not selected. Remove the guard and always select `INTEL_INT15` for simplicity. Change-Id: If51a0ab1c57b0856018a62cf669e5d1b53e5333c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/h61-series: Consolidate devicetree SATA optionsAngel Pons
The H61 PCH only supports 4 SATA ports, and does not support Gen3. Change-Id: I3e060ca6904fd6c773c322988a17bbca28333a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/h61-series: Relicense devicetrees as GPL-2.0-or-laterAngel Pons
I added these devicetrees in commit 65ddbb720b1 (mb/asus/p8h61-m_pro: Add new mainboard) and commit fe7c2b996bbb (mb/asus/p8h61-m_lx3_r2_0: Add new mainboard). To ease licensing matters when transforming these boards to use overridetrees, relicense the devicetrees so that all of them use the GPL-2.0-or-later license. Change-Id: Id26d0d9dd6cbb81d6a6a263feab7f36ddb4ff6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hexAngel Pons
Done for consistency with the other variants. Tested with BUILD_TIMELESS=1, Asus P8H61-M LX remains identical. Change-Id: I440706f6fa11d3c2410c445cb7e946c063578c4e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-20mb/asus/p8h61-m_lx: Transform into variant setupAngel Pons
Handle some differences in the DSDT code using preprocessor. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I2a02f32dfd9fa9c1adce3baf0d279ea19db5883f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-20mb/ocp/deltalake: Implement skipping TXT lockdown via VPDArthur Heymans
This allows to skip TXT Lockdown via "skip_intel_txt_lockdown" VPD parameter. Change-Id: Ic5daf96bdda9c36054c410b07b08bcd3482d777c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rocky Phagura Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-20mb/google/mancomb: Enable GFX HDA deviceIvy Jian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in mancomb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I47cf9a9dc73fd47e390b079bb9eaa14dc364404a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/google/guybrush: Add SoC thermal zoneRaul E Rangel
The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/asus/f2a85-m_pro: Set resources for 2e.bPaul Menzel
The v4 resource allocator logs the error below: […] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed) update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: f000, Tag: 100 PCI: 00:01.0 14 * [0x1000 - 0x10ff] limit: 10ff io PCI: 00:11.0 20 * [0x1100 - 0x110f] limit: 110f io PCI: 00:11.0 10 * [0x1110 - 0x1117] limit: 1117 io PCI: 00:11.0 18 * [0x1118 - 0x111f] limit: 111f io PCI: 00:11.0 14 * [0x1120 - 0x1123] limit: 1123 io PCI: 00:11.0 1c * [0x1124 - 0x1127] limit: 1127 io ERROR: Resource didn't fit!!! PNP: 002e.b 62 * size: 0x2 limit: fff io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done […] === Resource allocator: DOMAIN: 0000 - resource allocation complete === […] PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io PNP: 002e.b e2 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq PNP: 002e.b e4 <- [0x00000000f1 - 0x00000000f0] size 0x00000000 gran 0x00 irq ERROR: PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree […] So configure it, to use the resources from port 0. TEST=With CB:54669 boot Asus F2A85-M PRO to SeaBIOS/GRUB and Debian’s Linux 5.10.28 Solution-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: Ibfedca96e4b5ad17f99bc84e2fbf7d0a6aad4484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54670 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/kukui: Add rt1015 support for katsuSunway
Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb BUG=None BRANCH=kukui TEST=Speaker can work normally in katsu during firmware stage Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/sarien/var/sarien/hda_verb: Indent unindented commentsPaul Menzel
Change-Id: I2d08fa7506c6230491273f57ee0116927b29abe3 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/drallion/var/drallion/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). The file was an exact copy of `src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h` added in commit 95370e1f (mb/google/sarien: Add HD Audio verb table). Change-Id: I43cd73a14e07eb4518e3d44b6f81dff5016da721 Fixes: e3443d87 ("mb/google/drallion: Add new mainboard") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/sarien/var/arcada/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). Change-Id: Id8a099297bd8bcebf9734e1beee2449fdcca75c5 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/mancomb: Enable AMD I2S Machine DriverIvy Jian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. Also configure Audio Co-processor(ACP) to operate in I2S TDM mode. BUG=b:187860242 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I528f90d81a418236e512a1e0840ff44c3a3a983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20baytrail: Factor out INT15 handlerAngel Pons
The handler is the same on all Bay Trail mainboards. Factor it out. Change-Id: Ia1b6faaca4792cda5f14948d23498182bf4bb2c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54415 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/dedede: move discrete TPM in overridetree for lalalaAaron Durbin
Move discrete TPM in the devicetree to avoid emitting the following message: "Using default TPM ACPI path: '\_SB_.PCI0.LPCB'" There is no corresonding ACPI device for 1f.5 PCI device. Therefore, move the discrete TPM to a device that has the corresponding ACPI device node. Functionality should remain the same. BUG=b:187518267 Change-Id: Ie9ec70336d5651c87f06f8b357abd1bfdb1cc06b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-05-19herobrine: Enable macronix SPI configShaik Sajida Bhanu
Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19mb/google/brya/brya0: Manually probe fw_config for DB_LTETim Wawrzynczak
In order to use the USB WWAN module in USB mode (as opposed to PCIe), the PCIe RP must be turned off at the FSP level. The `probe` statement in the devicetree unfortunately takes effect too late, because the UPDs for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas fw_config probing for devicetree is done in ramstage. Add a new variant-specific file which will handle manually setting the UPD based on FW_CONFIG instead. BUG=b:180166408 TEST=set CBI FW_CONFIG field to LTE_USB, see message in console, set field to LTE_PCIE, do not see message in console. Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number, PLD and power_gpio for each DFP. BUG=b:186521258 TEST=Validated Retimer firmware upgrade along with upstream kernel under no device attached scenario. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I18f29ce5f8450a8b0f8208a60b8b607f9f0d8817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52714 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52711 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Disable dynamic GPIO PM for community 3Maulik V Vaghela
We recently added GPIO definition for PCIE vGPIO for Alder Lake. We also need to disable GPIO dynamic PM for this community which is already done for other communities as well. BUG=b:188392183 BRANCH=None TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also disabled Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/h61m-cs: Transform into variant setupAngel Pons
To preserve reproducibility, temporarily guard mainboard.c contents. This will be removed once all boards have become variants. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I1ffb41470d24713a4a7f0689958b733d4b1bdf52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_pro: Transform into variant setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_lx3_r2_0: Transform into variant setupAngel Pons
Get ready to squash all Asus H61 boards together, so as to factor out lots of redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I738197bf4d5ea8b879ae26ecbcb0cf3714316662 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/{h61m-cs,p8h61-m_lx}: Reorder `_PTS` and `_WAK`Angel Pons
Done to preserve reproducibility when switching to a variant setup. Change-Id: I78241c807f767846774b8e1a2e0d25f3452ed544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18Asus H61 boards: Align dsdt.asl with other boardsAngel Pons
Prepare to transform Asus H61 boards into a variant setup. Change-Id: Ifd5808edac22ebdba9b29a711ad129b91d9975d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18mb/asus/h61m-cs/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: I91ee7dc601f1fc52a7d68f66555143156b91ebf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54365 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 05:21:57 +0000