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2013-12-21Pit: set PWM to external on ParadeRonald G. Minnich
The PWM is controlled externally from the APU. Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61513 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4363 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: move parade writes to mainboard.cRonald G. Minnich
What gets written into the parade is highly mainboard-dependent. So the parade_writes array needs to be there. Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61486 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21peppy: Drive WLAN_DISABLE_L / BT_ON low in S3 and S5.Shawn Nematbakhsh
When the board is in S3 and S5 the WLAN_DISABLE_L signal can leak power into the WLAN power well since the GPIO controlling WLAN_DISABLE_L is in the suspend well. Therefore, drive WLAN_DISABLE_L low to avoid the power leak. This is a clone of a Falco change: I1a0df80dd47fdbd535aca7a9d49253794c480606. Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63220 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4383 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21FUI: Fill in link_m and link_n valuesFurquan Shaikh
... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy: remove unneeded code in i915io.cRonald G. Minnich
This code is left over from what the VBIOS did; It is redundant. Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62290 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4380 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Route USB to XHCI on resumeDuncan Laurie
Turn on the pei_data flag that will instruct the reference code binary to route all USB ports to the XHCI controller on resume and disable the EHCI controller(s). Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63798 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4404 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell boards: fix SATA interrupt in ACPIDuncan Laurie
SATA is routed to PIRQG which should be interrupt 22 and not interrupt 21. The kernel uses MSI with this device so this is only seen when booting with pci=nomsi Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63796 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: update ACPI C-state settingsDuncan Laurie
Since these boards do not support C10 we should not bother advertising that state in the ACPI _CST. Instead use this map: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint me: add support for mbp clear wait in finalize stepDuncan Laurie
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Revert "lynxpoint: Move ME lock down to ramstage"Duncan Laurie
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965. Deferring this step until the finalize stage will allow us to defer waiting for the MBP clear indicator and speeding up the boot. Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559 Reviewed-on: https://gerrit.chromium.org/gerrit/62631 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21SLIPPY: final changes for FUIRonald G. Minnich
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21peppy: Duplicate SPD data for 2GB configurations.Shawn Nematbakhsh
Peppy SPD table has 4GB configurations followed by 2GB configurations. Current implementation does remapping to point 2GB configuration to the same SPD index as the 4GB. This is different than Falco, which simply duplicates the SPD data for all configurations. To simplify probing in mosys, copy the Falco implementation of duplicating SPD data. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489 Reviewed-on: https://gerrit.chromium.org/gerrit/61847 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Jay Kim <yongjaek@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4369 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21haswell boards: Use PECI temp sensor id 0Duncan Laurie
The EC temperature sensors were renumbered and now PECI is at index 0. 1) boot on falco 2) check /sys/class/thermal/thermal_zone0/temp 3) check 'temps' on ec console Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61896 Reviewed-on: http://review.coreboot.org/4367 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21falco: Enable RTD2132 spread spectrum at 1.0%Duncan Laurie
This may need further tuning but will start at 1.0%. boot on falco and check /sys/firmware/log localhost ~ # grep RTD2132 /sys/firmware/log RTD2132: Enable 1.0% Spread Spectrum I2C: 01:35 (Realtek RTD2132 LVDS Bridge) Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61895 Reviewed-on: http://review.coreboot.org/4366 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21bolt: make the gpio interrupts edge sensitiveAaron Durbin
The drivers in the kernel expect the devices using gpios to generate interrupts to be edge sensitive. Make it so. Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61678 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4361 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-20armv7: Remove SYS_TEXT_BASE config.Hung-Te Lin
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory layout, remove it from current configurations. Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b Reviewed-on: https://gerrit.chromium.org/gerrit/61853 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4371 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-19ec/lenovo/h8: Enable 3G modemVladimir Serbinenko
Just like bluetooth and wlan it need to be enabled in EC. Set the appropriate bit in EC if CMOS config says so. Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4516 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-16X60/T60: Implement "next display output" button.Vladimir Serbinenko
Most of the code needed for this is already in the tree with X201 patch series but code didn't know where to send the next screen notification and so was disabled. Define right video device. Tested by: Sam Noble Change-Id: I4ff0d220afdca342617ce43c6e5d0164ad8eba27 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4494 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-15lenovo/x201: Add support for Lenovo X201 (Calpella-based laptop)Vladimir Serbinenko
Was extensively tested on my X201. More info on the wiki Change-Id: I503d77749780422e446b48224ca98a1f22a2c180 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4514 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-15intel/cougar_canyon2/Kconfig: Remove HAVE_ACPI_RESUME as S3 is unsupportedPaul Menzel
According to the commit message for the board Cougar Canyon 2 (48a749a8) resuming from S3 is currently unsupported. The FSP does not support S3 at this time. S3 may be added when it is available in the FSP. Mirror that in the configuration by not selecting the Kconfig option `HAVE_ACPI_RESUME`. Change-Id: I894f103ffa7d8db6342f99fff0867b02bc750752 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4519 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-12bolt: Initial mainboard commitDuncan Laurie
BUG=chrome-os-partner:20448 BRANCH=none TEST=emerge-bolt chromeos-coreboot-bolt Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59843 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4330 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12HDA: Enable Mini-HDA and fix up PCH-HDA initDuncan Laurie
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0 which uses the same verb table init sequence as the southbridge. In order to avoid two copies of the verb table loading code I separated out the HDA verb table functions into a file that can be re-used and then added a minihd driver to the haswell northbridge. The minihd verb table is the same across devices so it can live within the minihd driver rather than needing to be specified in each separate mainboard. I also fixed up the driver for lynxpoint HDA by following the reference code. Without HDMI cable plugged in driver does not find any codec, and it does not seem to re-probe when HDMI is connected. We may be missing kernel patches for this. hda-intel 0000:00:03.0: no codecs found! With a basic kernel patch to add 0x0a0c device ID to HDA driver and with HDMI cable connected it is much happier: snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9 snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10 input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11 Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12slippy/falco/peppy: make GPIO interrupts be edge triggeredDuncan Laurie
The drivers are designed to work with an edge triggered interrupt. Change-Id: I35a121ecfb6409bb9049f4d1e034185bb3bb7557 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4360 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12falco: drive WLAN_DISABLE_L low in S3 and S5Aaron Durbin
When the board is in S3 and S5 the WLAN_DISABLE_L signal can leak power into the WLAN power well since the GPIO controlling WLAN_DISABLE_L is in the suspend well. Therefore, drive WLAN_DISABLE_L low to avoid the power leak. Change-Id: I1a0df80dd47fdbd535aca7a9d49253794c480606 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61421 Reviewed-on: http://review.coreboot.org/4358 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12exynos5420: Setup clocks for MMC bus controller.Hung-Te Lin
To configure source clocks on Exynos 5420 for MMC drivers. Some registers are different from the 5250. FSYS now has two parts and MMC uses FSYS2. The MMC block uses MPLL as the clock source. The "high-speed" MMC interface runs as 52MHz, so divider is set accordingly. Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller Interface) to DWMCI (DesignWare MMC Controller Interface). Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60858 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4354 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: Add backward-compatible RAM_ID table.Shawn Nematbakhsh
Make use of google_chromeec_get_board_version to determine board version, and apply proper RAM_ID table to load correct SPD. Change-Id: I6a2d54759cf2ce98bf53df0db396c6e09368c714 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61192 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4353 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12Peppy: Update Realtek ALC283 verb tableMartin Roth
Update peppy's verb tables for the Realtek ALC283 Audio Codec. ALC283 Configuration: Digital Mic - NID 12h: Disabled Speakers - NID 14h: Enabled Mono out - NID 17h: Disabled Mic 1 - NID 18h: Disabled Mic 2 - NID 19h: Headphone Jack Line1 - NID 1Ah: Internal Mic Line2 - NID 1Bh: Disabled PCBEEP - NID 1Dh: Enabled SPDIF - NID 1Eh: Disabled HP-OUT - NID 21h: Headphone Jack Mic 1 doesn't seem to really be available, but the documentation refers to NID 18h as MIC1, so it's being disabled as it's not being used. The onboard microphone has been moved to line 1. I had my peppy modified to attach the mic to line1 and mic1 now works with this patch. Mic2 looks harder to rework, so I think that will have to wait for the DVT boards. Change-Id: I7d6ce6b428806b6aed1d36e7e25302fa5ae14b21 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/58880 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12falco: fix usb port settingsDuncan Laurie
USB2 Port A set to 6.4" and Back Panel USB2 Port B set to 5.2" and Back Panel USB2 Port C set to 12.3" and Internal Other devices all set to Internal. build and boot on falco and check settings. Based on the config settings all ports end up with tuning param 1 == 5 and param 2 == 2 U2ECR[0] = 0x00059501 U2ECR[1] = 0x00059501 U2ECR[2] = 0x00059501 U2ECR[3] = 0x00059501 U2ECR[4] = 0x00059501 U2ECR[5] = 0x00059501 U2ECR[6] = 0x00059501 U2ECR[7] = 0x00059e01 Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61297 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4350 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12falco: Remove thermal thresholds that use CTDPDuncan Laurie
This CPU does not support Configurable TDP and so far does not need to use Controllable TDP. Change-Id: I15599cd4e6890dd5c9d9f99bc4e95307a8dcc827 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60657 Reviewed-on: http://review.coreboot.org/4347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12PIT: remove a comment that is incorrect.Ronald G. Minnich
The is_resume comment is wrong for this board. It only applies to the older 5250 cpu. In fact, the is_resume parameter is not needed for ddr init and will likely be removed soon. Change-Id: I4e3c92fcaaa75d3c9223d90acccf053f61406307 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60103 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4342 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12snow: Fix the edid data structure definition so depthcharge works again.Gabe Black
Some new fields were added to the edid data structure, and the edid code was changed to put estimated values into those fields which were ultimately passed into depthcharge or other payloads. On snow we do things different and just declare an edid structure statically which didn't have those members. The rows and columns of the graphics console were 0, and that confused the framebuffer driver and made it loop forever. Change-Id: I6ca3bd948482b347a6a981e83b82b10dca995e5e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61057 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: RAM_ID + storage changes for next build.Shawn Nematbakhsh
- Update RAM_ID table. - Add DEVSLP0 signal to NGFF SATA port. Note: After this change, old Micron 2GB boards will no longer boot. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id68a1d6ace2702cca9c37305726cd55a0bde5005 Reviewed-on: https://gerrit.chromium.org/gerrit/60167 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4340 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: Disable audio codec enable GPIO in S3 + S5.Shawn Nematbakhsh
To save power, disable audio codec in S3 + S5. Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM binary. Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60950 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4339 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-07peppy: Enable power limiting for thermal controlDuncan Laurie
Limit power to 12W at 73C and remove limit at 68C. To have the CPU consume maximum power it is necessary to stress both the CPU and the GPU. Bastion (chrome.supergiantgames.com) and/or webglsamples.googlecode.com can be useful for this. Testing this properly requires a script to report the running average power readings. The watch_power.sh script is attached to this issue in the partner tracker. 1) Run watch_power.sh continuously: localhost ~ # watch -n 0 bash -e /tmp/watch_power.sh 2) Start Bastion (or other stress apps). The power draw should be close to 15W if under enough load. 3) Watch until temperature climbs above 73C and is caught by the thermal zone 10 second poll, this can be sped up by blocking or removing the fan. 4) The ACPI thermal zone states should change to reflect that active[2] is now enabled and power consumption should drop to 12W. 5) Stop the stress apps and wait until the CPU cools off again, enable the fan again if it was removed. 6) The ACPI thermal zone state should switch back to active[3]. Change-Id: Ie6714a8543d4f06edf8513086fc9c968273bdb23 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60545 Reviewed-on: http://review.coreboot.org/4335 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-06butterfly: Fix build without ChromeOSKyösti Mälkki
Use a file in CBFS for keyboard layout and ethernet MAC instead of scanning FMAP. Change-Id: I7658c7c4e389deb20d7d8f57cce8b568efdc575d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06qemu: fix GENERATE_ACPI_TABLES=n in fw_cfg.cGerd Hoffmann
Change-Id: Ib8dc069c9e503747c349e96a466feb42279afd08 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05google/link: use the new edid functions when in FUI modeRonald G. Minnich
The new edid functions support converting the edid to an lb_framebuffer. Use them. Also, since panels seem to set bits per color instead of bits per pixel, just force the right value in the edid struct. Add helpful comment because people don't always believe we need to set the pallette. While we're at it, fix a problem that caused it to not compile. Change-Id: I645edc4e442d9b96303d9e17f175458dc7ef28b6 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/57619 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05peppy: Disable forced dev mode.Shawn Nematbakhsh
Don't force dev mode. Allow users to enter / exit dev mode as normal. Change-Id: I168eb04a8ac102a8c4a1ca8936f78f62b001e0eb Reviewed-on: https://gerrit.chromium.org/gerrit/59492 Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4321 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05Fix Makefile to include all copies of the SPD sourcesDuncan Laurie
On some systems there may be 2GB SKU that is the same as the 4GB SKU but just one channel of memory. In that case we need to ensure that both copies of the same SPD source end up populated by ensuring that repeated entries are included by using $+ instead of $^. Alternatively we could do the check inside romstage, but it is already set to behave this way if the SPD gets populated correctly. I changed spd_index to 3 in falco romstage to force it to pretend it was a 2GB config of the same memory, then booted to ensure it was indeed limited to 2GB. memcfg channel[0] config (00780008): ECC inactive enhanced interleave mode on rank interleave on DIMMA 2048 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00600000): ECC inactive enhanced interleave mode on rank interleave on DIMMA 0 MB width x8 single rank, selected DIMMB 0 MB width x8 single rank Change-Id: Ibfe5051ccda2fe69e8caff3f3c264116e3411c65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59483 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Jay Kim <yongjaek@chromium.org> Reviewed-on: http://review.coreboot.org/4319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'Zheng Bao
Propagated from http://review.coreboot.org/3347 http://review.coreboot.org/3374 The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4261 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05AMD Kabini: Add ACPI sleep/wakeup calls for southbridgeZheng Bao
The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT even it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4260 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-04lenovo/x60: Drop global oprom_is_loadedKyösti Mälkki
Variable use is specific to ChromeOS. Change-Id: I5b61a038e6b08e3b2408c4d990749d45fdf2148d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4306 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-04lumpy: Fix build without ChromeOSKyösti Mälkki
Change-Id: I1a59405499deceed7df01a03834be72830e6578f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-04intel/cougar_canyon2: Intel CRB FSP based mainboardMarc Jones
Cougar Canyon 2 is a Ivybridge/PantherPoint reference board. This implementation uses the Intel FSP (Vist the Intel FSP website for details on FSP architecture and support). The FSP does not support s3 at this time. S3 may be added when it is available in the FSP. All other features and IO ports are functional. Booted on Ubuntu 12.04 and 13.04, Fedora 18 with SeaBIOS payload. Memtest86, FWTS, and other tests pass. Board support page will be updated on acceptance. Change-Id: I26c0b82d7ac295498376ad4c3517a9d6660d1c01 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03qemu-armv7: Drop additional console_init()Stefan Reinauer
It's done in bootblock_simple.c just after returning from the mainboard specific bootblock function. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I96cab5e406132a9f7dc30d48ff99f524773a1a14 Reviewed-on: https://gerrit.chromium.org/gerrit/58473 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4257 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03slippy/falco/peppy: Fix Chrome OS GPIO export in ACPIDuncan Laurie
The OIPG package needs to have >1 member to make the chromeos_acpi kernel driver do the right automagic sysfs topology creation. Additionally an "unimplemented" GPIO should be reported as 0xFF because 0 is a valid GPIO number. verify crossystem on slippy $ sudo crossystem | grep -e recoverysw_cur -e wpsw_cur recoverysw_cur = (error) wpsw_cur = 1 Change-Id: I06dff09152bde30a3ffe58b1defe9d299155472c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57471 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4221 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-03haswell boards: Enable VIRTUAL_DEV_SWITCHDuncan Laurie
This config option was not enabled which was preventing the user from enabling developer mode from recovery mode. With this enabled we can disable the "dev mode by default" behavior and let people enable it by entering recovery mode. This will make the firmware behave like a typical chromeos device. Peppy is left in "default dev mode" until after bringup. 1) boot slippy in normal mode by default 2) enter recovery mode with servo button 3) Ctrl+D on USB keyboard to enter developer mode 4) boot slippy in developer mode Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57350 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4220 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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