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2013-03-13src/mainboard: Drop redundant `CHIP_NAME` again for new portsPaul Menzel
Since commit »Drop redundant CHIP_NAME in mainboard.c« (a93c3fe7) [1] `CHIP_NAME` is unneeded for mainboards as the name is composed automatically in `src/devices/root_device.c` from the strings in Kconfig. Unfortunately the ports for Google Butterfly, Link and Parrot as as well as IEI PM-LX2-800-R10 introduced CHIP_NAME again. So drop it again too. [1] http://review.coreboot.org/1635 Change-Id: Ice7577a2a5c6070e196f2647c440b7a8e140e27e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250/snow: call PMIC's power_init() functionDavid Hendricks
Call the power_init() function. We appear to have forgotten about it when deprecating lowlevel_init_subsystems(), but it didn't seem to cause problems until we got to doing more interesting stuff recently. There are some clean-ups to do from the original code, such as not attempting to configure I2C from PMIC code, which we'll get around to in follow-up patches. (Credit to Gabe for spotting this) Change-Id: I6a59379e9323277d0b61469de9abe6d651ac5bfb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2699 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-11ASUS M5A88-V: Kconfig: Fix mainboard model namePaul Menzel
Despite everywhere the model name M5A88-V is used, in Kconfig the string M5A88PM-V is used. Searching for that model string on the WWW does not return anything which is unrelated to coreboot, so change that string to M5A88-V. Change-Id: I25cf9d4a5fc3f9b9356e8616452066ebf873f44c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: QingPei Wang <wangqingpei@gmail.com>
2013-03-08Persimmon DSDT: Add secondary bus range to PCI0Mike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This change will apply to other AMD mainboards and will be in a different commit. Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AMD Inagua: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the inagua mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2607 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD CIMx SB800 boards: platform_cfg.h: Integrate Kconfig SATA Mode choicePaul Menzel
Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V despite what is chosen in Kconfig »Chipset« menu item, $ more .config […] # CONFIG_ENABLE_IDE_COMBINED_MODE is not set CONFIG_IDE_COMBINED_MODE=0x1 # CONFIG_SB800_SATA_IDE is not set CONFIG_SB800_SATA_AHCI=y # CONFIG_SB800_SATA_RAID is not set CONFIG_SB800_SATA_MODE=0x2 […] the SATA controller is put into IDE mode. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40) Commit »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [1] added the options above to configure the mode using Kconfig and some SB800 boards were adapted already. For example commit »persimmon: sb800 sata mode configure update« (1386fa74) [2] did so for AMD Persimmon. Doing the same by assigning the Kconfig variable to the value in `platform_cfg.h` integrates this with the three remaining boards listed above. The patch is successfully tested with the ASRock E350M1. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40) [1] http://review.coreboot.org/225 [2] http://review.coreboot.org/227 Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08AMD Persimmon: mainboard.c: Make comment generic to reduce differencePaul Menzel
Replace »persimmon« by »board« in comment to keep `diff` output between boards small. Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08AMD Union Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the union_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I19d6b0d674b67294519383f80928471b37da1e14 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD South Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the south_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08ARMV7 and Google/Snow: Add exception support code to the ramstageRonald G. Minnich
This is previously used exception code from libpayload. On startup it installs and then tests an exception handler. The test is an unaligned memory operation. Yes, we've seen what might be exceptions in the ramstage, and it makes sense to handle them. This code is identical in structure and operation to the previously committed payload exception handler, though we reserve the right to change it as circumstances require. The remaining question is whether we need it in romstage. Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-08Supermicro H8QGI: set up right frequency limits for memory controllerKonstantin Aladyshev
According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08FrontRunner/Toucan-AF: lower SPI speed to 22 MHzJens Rottmann
The Hudson-E1's default SPI speed for normal i.e. non-fast reads is 66 MHz, but the SST 25VF032B datasheet allows max. 25. Lower the speed to 22 MHz, otherwise BIOS flashing fails. Change-Id: I22e87d833a3ebd316b6e873595a2480831533ab1 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2605 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07AMD Persimmon: Use SPD read code from F14 wrapperMartin Roth
Changes: - Get rid of the persimmon mainboard specific code which has been moved into the wrapper as a platform generic function in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2500 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07snow: add real values for GPIOs in fill_lb_gpios()David Hendricks
This adds some real GPIO mappings where virtual GPIOs were used before. Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07google/snow: fix coding styleStefan Reinauer
cosmetics Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2601 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-07ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`Paul Menzel
Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2489 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2013-03-06samsung/exynos5: add display port and framebuffer defines and initializationRonald G. Minnich
These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2570 Tested-by: build bot (Jenkins)
2013-03-06ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`Paul Menzel
Since the merg of the ASRock E350M1 port (a649a96e) the compiler warns about the following [1]. mainboard.c:35, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_reset' [-Wmissing-prototypes] mainboard.c:43, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_dereset' [-Wmissing-prototypes] Adding the function prototypes to the beginning of the file as done in commit »Persimmon updates for AMD F14 rev C0« (d7a696d0) addresses the warning. [1] http://qa.coreboot.org/job/coreboot-gerrit/4975/warnings13Result/package.-139448264/file.-1544928473/ [2] http://review.coreboot.org/137 Change-Id: Iad2e62ec37c3a2f749a264974b61ac7c226e9b83 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-06Google/Snow: enable sound hardware clocksRonald G. Minnich
Set up the clocks used for sound and turn on the sound clock. Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8 Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2587 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06google/snow: Change MMC0 to work in 8 bit mode.Ronald G. Minnich
The MMC0 on google/snow can run in 8 bit mode. To simplify driver development, we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help. However, after some experiments in payload drivers, setting pinmux to 8 bit mode can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable 8 bit mode by default for better performance. Verified to boot on google/snow, and got MMC0 working. Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2585 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-04FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selectionJens Rottmann
The first reason for selecting the CPU model at compile time was a multi-second pause if booting a single core Fusion T40R with MAX_CPUS=2. Recent tests show the pause has disappeared, someone must have fixed it. The second reason was me not knowing how to make a single vgabios image work with two different PCI IDs. Many thanks to Martin Roth for educating me! Quote: "The way to make coreboot use the same vbios for different video device IDs is through the map_oprom_vendev function. In family 14 it's in northbridge/amd/agesa/family14/amdfam14_conf.c You would name your video bios 1002,9802 in the config and all the other device/vendor IDs for the family 14h processors will fall through the initial check for the video bios and will get remapped to use that vbios. This only works if you're initializing the vbios inside coreboot. I don't know if you're using SeaBios as a payload, but if you are you can add the vbios to cbfs as vgaroms/vbios.rom and the rom will always be initialized." I'd like to add the vgabios is added as type 'optionrom' when Coreboot make adds it, however to work with SeaBios it has to be added manually with cbfstool and with type 'raw', or it will hang. Change-Id: I8190d0c3202a60dfccb77dde232f9ba7ce5ce318 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2584 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-03AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in commentPaul Menzel
Commit f154c018 Author: Marc Jones <marcj303@gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2576 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-02ASRock E350M1: Remove non-existing PCI devices 12.1 and 13.1Paul Menzel
Looking at the coreboot log […] PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled […] and the `lspci -tnvv` output running the proprietary vendor BIOS attached to the Wiki page of the ASRock E350M1 [1][2] -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-04.0-[01]-- +-11.0 1002:4391 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 […] both PCI devices do not exist, so remove them from `devicetree.cb`. Commit 48918f7 [3] Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does did the same for AMD Inagua and AMD Persimmon. [1] http://www.coreboot.org/ASRock_E350M1 [2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2 [3] http://review.coreboot.org/2463 Change-Id: Ief6de1bda093d1f29d5925985e5c3839cdded537 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2536 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-02FrontRunner/Toucan-AF: work around AGESA RAM init crashing on rebootJens Rottmann
If you try to reset the system with outb(3,0x92), outb(4,0xcf9) or a triple-fault it will instead crash with a messy screen. As the more common outb(0xFE, 0x64) doesn't work with our setup, Linux will crash whenever you ask it to reboot. Closer inspection shows that on a warm boot of Coreboot agesawrapper_amdinitpost() always fails with error code 7. Looks like DDR3 re-init goes wrong somehow. I tried find the reason for this but was unable to. I am convinced this is not board specific but a bug in AGESA. In the end I had to settle for a workaround: if amdinitpost returns 7 this patch resets the system harder with outb(0x06, 0x0cf9), after that RAM init will succeed. As amdinitpost is early in POST this automatic reset is quick enough not to be noticable. I'd perfer a real fix, but that's all I have. Change-Id: I4763254b489f42a135232e45328ecf0d5c4d961a Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2573 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT Toucan-AF [2/2]: actually implement mainboard supportJens Rottmann
Step 2: change the Persimmon code to adapt it to the new board's hardware. The Toucan-AF is a COM Express Compact Type 6 form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU - 1-4 GB DDR3 memory down - 1x VGA, 2x DisplayPort (1 switchable to LVDS) - AMD A55E (Hudson-E1) southbridge - 8x USB 2.0 - 4x SATA - HD Audio (with codec on baseboard) - NEC uPD78F0532 microcontroller on I2C ("SEMA") - 7x PCIe2.0 x1 (1 on PEG) - Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe) - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS) The Toucan-AF has no SIO on board. This patch includes basic support for a Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used for evaluation happens to have one. The code may have to be adapted to the actual baseboard of the application. http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT Toucan-AF [1/2]: create board by forking AMD PersimmonJens Rottmann
Step 1: copy all files unmodified from Persimmon. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Git's copy detection is imperfect (and slow). Change-Id: I1ff02913479c07679f8c3ae5e6dd7876e6000b55 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT FrontRunner-AF [2/2]: actually implement mainboard supportJens Rottmann
Step 2: change the Persimmon code to adapt it to the new board's hardware. The FrontRunner-AF is a PC/104+ form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU - DDR3 SO-DIMM socket (1.5 or 1.35V) - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0 - 1x SATA, 1x CFast socket - HD Audio (via Realtek ALC886) - PCI and ISA (via ITE IT8888) - NEC uPD78F0532 microcontroller on I2C ("SEMA") - Intel I210 GbE (on APU PCIe x1) - SMSC SCH3112 SIO - PS/2 - 2x RS232/485 - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS) http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131 Change-Id: Id55f89d224ad669b351c36128b12299802b721ba Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT FrontRunner-AF [1/2]: create board by forking AMD PersimmonJens Rottmann
Step 1: copy all files unmodified from Persimmon. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Git's copy detection is imperfect (and slow). Change-Id: I2fd1bf8428fc8a1e7becee888b6182b9bd8166a0 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2552 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01armv7/snow: Add S5P MSHC initialization in ROM stage.Hung-Te Lin
The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and pinmux settings before it can be detected and used in ramstage / payload. Verified on armv7/snow and successfully boot into ramstage. Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28CBMEM: always initialize early if the board supports itStefan Reinauer
This allows to drop some special cases in romstage.c Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Drop SRC_ROOT from mainboard Makefile.incsStefan Reinauer
It's not used, and not needed. Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Google/snow: update the GPIO emulation.Ronald G. Minnich
Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2538 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-02-27Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cbJens Rottmann
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.) turned off the device in AGESA. Now remove it from devicetree.cb, too. This prevents the following boot message: PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. Also clarify the line's comment a bit for the Fam14 boards which still retain this device (to counter the loss of information ;-). Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2537 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-27Mainboard SMI S state handler was using the wrong definesMarc Jones
The PCH register bit definition for sleep type is a little confusing. For example, 7 is S5. To make this simpler for the mainbaord developer, the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2). A couple mainboard SMI handlers were using the PCH define for slp_ty, so S3 code would be run for S5 and S5 code would never be run. Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-26AMD Inagua: buildOpts.c: Adapt whitespace to coding stylePaul Menzel
Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the other boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AMD Fam14 boards: reduce unnecessary differences, 2nd attemptJens Rottmann
This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-25Supermicro H8SCM & H8QGI: Fix printk warningsMartin Roth
Changes: - Fix printk warnings for these two platforms by getting rid of the l length specifier and casting to unsigned int. This gets rid of a bunch of warnings like this one: agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Notes: - This is the same change that was done for Tyan s8226 in change: ddff32eb - http://review.coreboot.org/#/c/2451/ Tyan S8226: Fix printk warnings - I have not tested this change on either of these platforms, I have just compiled it. Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Southstation: Fix final warningMartin Roth
Changes: - Add #include of delay.h in mainboard.c to pick up declaration of mdelay function. Notes: - This fixes this warning: mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal implicit declaration of function 'mdelay' [-Wimplicit-function-declaration] Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2501 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Fam14 boards: Set P_BLK length to 6 for all processorsPaul Menzel
Currently on for example on AMD Persimmon and ASRock E350M1 Linux complains, that the PBLK length is invalid [1]. ACPI: Invalid PBLK length [0] Consequently, frequency scaling might not work correctly, though for these two boards it seems to work according to PowerTOP. Indeed, according to the ACPI specification [2], setting PBlockLength to 0 is only allowed if there is no PBlockAddress. Otherwise it has to be set to 6. 18.5.93 Processor (Declare Processor) […] PBlockAddress provides the system I/O address for the processors register block. Each processor can supply a different such address. PBlockLength is the length of the processor register block, in bytes and is either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0. And that is exactly what Linux is checking in `drivers/acpi/processor_driver.c` [3]. static int acpi_processor_get_info(struct acpi_device *device) { […] /* * On some boxes several processors use the same processor bus id. * But they are located in different scope. For example: * \_SB.SCK0.CPU0 * \_SB.SCK1.CPU0 * Rename the processor device bus id. And the new bus id will be * generated as the following format: * CPU+CPU ID. */ sprintf(acpi_device_bid(device), "CPU%X", pr->id); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, pr->acpi_id)); if (!object.processor.pblk_address) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n")); else if (object.processor.pblk_length != 6) printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n", object.processor.pblk_length); else { pr->throttling.address = object.processor.pblk_address; pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset; pr->throttling.duty_width = acpi_gbl_FADT.duty_width; pr->pblk = object.processor.pblk_address; /* * We don't care about error returns - we just try to mark * these reserved so that nobody else is confused into thinking * that this region might be unused.. * * (In particular, allocating the IO range for Cardbus) */ request_region(pr->throttling.address, 6, "ACPI CPU throttle"); } […] } This issue has proliferated to all AMD based boards so fix it for all of them by setting P_BLK length to 6. The DSDT of for example AMD Parmer and AMD Thatcher also set it to 6 everywhere so this solution is taken instead of setting the P_BLK system I/O base to 0 for all but the first processor which is how it is done for earlier AMD based boards. As note having to set this manually should not be needed and this should be autogenerated as done for most of the Intel boards and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`). [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351 Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • ASRock E350M1: Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • AMD Persimmon: Tested-by: Martin Roth <martin.roth@se-eng.com> Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2189 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-25Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) doesJens Rottmann
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1 simply does not exist, so remove it from devicetree.cb. While at it make the comment more detailed. Likewise for all USB ports. USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off). Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID fieldPaul Menzel
The DSDT header contains the fields OEMID and OEM Table ID. See for example ACPI specification 4.0a [1] 5.2.11.1 Differentiated System Description Table (DSDT) on page 135. There Table 5-16 contains the descriptions. Field Byte Length Byte Offset Description =================================================== OEMID 6 10 OEM ID OEM Table ID 8 16 The manufacture model ID. Currently in coreboot there is no common method what to put in these fields. Mostly Intel based boards populate it with "CORE " ore "COREv4" and AMD based boards populate it with the board vendor and model number, abbreviated appropriately to fit into these fields. On most boards the proprietary vendor BIOS seems to leave these fields – displayed with `sudo dmidecode` under System Information – blank To Be Filled By O.E.M. and fill out the Base Board Information with the board vendor and model name. In [2] Jens Rottmann argues that the this is really just the table ID used for naming it and that »99% of the DSDT code is not board specific«. Both approaches seem to have their advantages, but using the second one, developers often seem to forget to update them (for example AMD Thather). The current situation is at least not optimal. and therefore at least unify the string in the OEM Table ID. If unifying the OEM ID is also a good idea this should be done too. If later on it should be decided that the board vendor and model should be used again, this should be somehow derived from Kconfig. The following command was used for the change [3]. $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/' This patch is split out from [2]. [1] http://www.acpi.info/spec40a.htm [2] http://review.coreboot.org/#/c/2464/ [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2472 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25QEMU x86: northbridge.c: Name enabling device function to `northbridge_enable`Paul Menzel
Similar to the discussion on the coreboot list [1] Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge: […] > Function names should try to be descriptive. "enable_dev" is not very > descriptive. I like "mainboard_enable" because it makes output such > as > > printk("%s: foo", __func__); > > useful. rename the function for the northbridge to `northbridge_enable`. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html Change-Id: I262311ec511e394550330214621b8c37780c1d4e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2496 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Persimmon: Fix warning, enable warnings as errorsMartin Roth
- Fix redefinition warning for SB_GPIO_REG50 introduced in commit fa8702cf - http://review.coreboot.org/#/c/2446/ Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon The warning being fixed is: SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal "SB_GPIO_REG50" redefined [enabled by default] - Enable warnings as errors so no more warnings will be accidentally committed. Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2494 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25mainboard.c: Name enable_dev function uniformly `mainboard_enable`Paul Menzel
To reduce the differences between these file name the enabling device function in the directory `src/mainboard` uniformly `mainboard_enable` [1]. Thanks to the awesome help of gnomon and BlastHardcheese in the IRC channel #sed on <irc.freenode.net>. gnomon came up with the following command to do the actual work. $ cd src/mainboard $ for f in */*/mainboard.c ; \ > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \ > [[ -z $src ]] && continue ; \ > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \ > done `src/mainboard/digitallogic/msm586seg/mainboard.c` and `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted manually as no comma was used separating the struct members. And with the following statement, gnomon is even more likable! My pleasure entirely. Good luck with coreboot; I'm a big fan of the project. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2493 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Technologic TS5300: mainboard.c: Move { to next linePaul Menzel
This is coreboot’s coding style. Change-Id: I7441f2c1927a49a3b7171112b7798dae6b56cfb5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2492 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-24Siemens SITEMP G1P1: mainboard.c: Rename `init` to `mainboard_init`Paul Menzel
This is the common way to name that function, so unify that. Change-Id: I8a01051bd304039662894b89eed53ce14dde98b6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-23Add support for Google's Chromebook PixelStefan Reinauer
Ladies and gentlemen, I'm very happy to announce coreboot support for the latest and greatest Google Chromebook: The Chromebook Pixel. See the link below for more information on the Chromebook Pixel, and its exciting specs: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel The device is running coreboot and open source firmware on the EC (see ChromeEC commit for more information on that exciting topic) Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2482 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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