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2017-09-05mb/google/soraka: Camera PMIC run time power controlNaresh G Solanki
Currently PMIC (tps68470) is in active state even when cameras are not in use. PMIC is put into SLEEP mode only when entering S3 via smihandler. With this change PMIC will be put into SLEEP mode as soon as sensors & VCM voltage outputs are turned off. This will allow run time power saving when camera is not in use. PMIC will be reset in first boot & across S3 & S0ix cycles. Also, remove the smi handler for PMIC power management & handle it as part of sensor and VCM ACPI PowerResource. BUG=b:63903239 TEST= Build for Soraka. Check Camera probe, Capture image across S3 & S0ix cycles. Also checked the following & found no regression: 1. Typical camera use cases 2. Stability tests related to camera 3. Reliability tests related to camera 4. PnP tests related to camera 5. Latency related tests with camera Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05mainboard/intel/harcuvar: Add support for Intel Harcuvar CRBMariusz Szafranski
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC ("Denverton" and "Denverton-NS") for the communications segment/market. The MohonPeak coreboot was used as the starting template with additions/modifications from other Intel Apollo Lake/Skylake coreboot. Tested with TianoCore payload (UDK2015) and Poky (Yocto Project Reference Distro) 2.0 with kernel 4.1.8 booted from SATA drive and external USB pendrive. Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-02mainboard/google/fizz: Enable support for DPTFTsai, Gaggery
This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for fizz. It also enables the DPTF flag in the device tree for fizz. BUG=b:64915426 BRANCH=None TEST=emerge-fizz coreboot and run DPTF observation tool to make sure DPTF is up and running. Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-02mainboard/google/soraka: Remove wacom digitizerWisley Chen
We have no wacom digitizer on I2C#3, so remove it. TEST=build and boot on soraka. Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21309 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-02mb/hp: Enable ExpressCard hotplug in all ElitebooksIru Cai
The MPC.HPCE bit of the ExpressCard root port is not set in vendor firmware, so autoport didn't generate the right pcie_hotplug_map to support ExpressCard hotplug. Also add comments for each PCIe root port. Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/21310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-01intel/i440bx: Move LATE_CBMEM_INIT under mainboardKyösti Mälkki
Some of these will move to EARLY_CBMEM_INIT. Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
2017-09-01lippert/toucan-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/frontrunner-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31google/gru: Support Nefario rev0Philip Chen
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario. Also, remove DVS support for CENTERLOGIC. BUG=b:64702054, b:63537905 TEST=build coreboot Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/21176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-31lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31lenovo/g505s: Enable XHCI device in devicetreeKyösti Mälkki
Enabling XHCI is additionally controlled with Kconfig option HUDSON_XHCI_ENABLE. Even when it is enabled, it EHCI debug works on the USB port next to the DVD drive door. Change-Id: I83738da6015f58ecd0819c553d333a176365dc78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31lenovo/g505s: Switch from f15rl to f15tnKyösti Mälkki
Support code for Trinity and Richland is identical now. I have also come across a unit with Trinity model CPU, whose CPUID was not listed in f15rl while f15tn already had support for f15rl. Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-30mainboard/google/soraka: Add stop gpio control to touchscreen deviceFurquan Shaikh
BUG=b:64987428 TEST=Verified that touchscreen works on boot-up and after suspend/resume. No power leakage via stop gpio in suspended state. Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-30mainboard/google/soraka: Remove Atmel TouchscreenFurquan Shaikh
We no longer use this touchscreen device, so get rid of it. BUG=b:64987428 Change-Id: I67af787d231317a80998fb483eed5674de19aeb4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30google/cyan: update SPD functionsMatt DeVillier
Update cyan's SPD-related functions to more closely mirror those of other Braswell boards, in order to simplify the upcoming baseboard/variant setup for Braswell ChromeOS boards. TEST: boot google/cyan, observe SPD correctly identified in cbmem log, RAM-related data correct in SMBIOS tables. Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-30drivers/i2c/ck505: Add generic driver to configure clockgenArthur Heymans
Replaces the ics/954309 driver with a more generic version to accommodate clockgens with a different amount of registers. It also features a mask to only touch certain bits of the clockgen. TODO: set appropriate mask for X60/T60 since the datasheets for their clockgens can be found. Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-30mb/google/eve: rt5514: Add 16ms delay on dmic initDuncan Laurie
Add a 16ms delay to DMIC init by the kernel driver in order to prevent an audible 'pop' noise when starting to record. BUG=b:63413023 TEST=manual testing to ensure this device property is present in SSDT: Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package () { "realtek,dmic-init-delay", 0x10 } } }) Change-Id: If9160ce6992153ba49719029de336595bbf4ae72 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-29mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 393 - 397 I2C1: 393 - 400 I2C2: 392 - 400 I2C4: 392 - 400 I2C5: 392 - 400 Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-28mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelistKevin Keijzer
TESTED on Lenovo T400 Change-Id: I365aeb7e997def225c23d3287558bdc4eefa4298 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/21230 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28google/Bruce: Add Raydium touch screen supportSheng-Liang Pan
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/21233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28mainboard/winnet/g170: Add ACPI supportLubomir Rintel
What is present is APIC and legacy interrupt routing and the soft-off sleep state. Other sleep states are missing, so are the SuperIO devices. Boots Linux with and without "noapic" and a Windows XP (installed with factory BIOS, the installer reportedly requires legacy keyboard). Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Initialize the IRQ routingLubomir Rintel
Initialize IRQ routing for legacy non-PNP OSes the same as the factory firmware would do. Change-Id: I0c7a7d584a2c47471456ab54ef6da815a2dc4e7c Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Add WinNET G170 boardLubomir Rintel
Change-Id: I0d7aba827fb87f69f542edd2f7ac7a66d949f865 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Copy from mainboard/bcom/winnetp680Lubomir Rintel
G170 is a board manufactured by WinNET, used in thin clients including HP Neoware CA19 and IGEL 2110. Copied from mainboard/bcom/winnetp680 which seems to be a similar board with an extra PCI slot. The p680 should probably be moved to winnet/ too, since the board is an OEM WinNET board, with BCom being just a machine that happens to it. Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mb/gigabyte/ga-b75m-d3*/acpi: Remove redundant codePatrick Rudolph
Remove obsolete code. The same settings are always done in southbridge. Change-Id: Ic893ddbace73ae8b122c4fb675febc7d1e0b5da9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28AGESA f15: Remove f10 referencesKyösti Mälkki
Vendorcode for f15 also has f10 support, so AMD_AGESA_FAMILY_10 was never selected. Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 375 - 400 I2C1: 377 - 400 I2C2: 377 - 400 I2C4: 375 - 397 I2C5: 375 - 397 Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-27mb/lenovo/*/acpi_tables: Add critical and passive thresholdPatrick Rudolph
Add critical and passive threshold to be advertised in thermal zone 0. Change-Id: Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-25jetway/nf81-t56n-lf: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I6ad0c4cf2f0398f0b1efac1282822acf0d4a3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/union_station: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I706de64ae5d940df70701c8b9dd717f8e212cd0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/south_station: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I09fe0e903a1241212f81e2a897898356a7e372a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/persimmon: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: Id2ef3e5aa0ea3f6e714eda6d9dbdf62fb96c0a74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/inagua: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: Ie76291a8e227e49aae6fc6339cec2009ebd67fff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25elmex/pcm205400: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: Ib386b5d9ba636614016c3f9ac042fee43eac53f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25asrock/e350m1: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I6ad99af55975b21b0a7671553246cdb5a1e19091 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25gizmosphere/gizmo: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I26e2450babfde1580e0e794c519344112d4019ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25pcengines/apu1: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I10b3e53a5e39764e3b199561d07391779804407c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25google/beltino: fix LED polarity for mccloud variantMatt DeVillier
The LED polarity was set incorrectly, fix using values derived from original Chromium sources: branch firmware-mccloud-5827.B, ToT src/mainboard/google/mccloud/smihandler.c src/mainboard/google/mccloud/romstage.c TEST: boot google/mccloud, observe power LED on normally, blinking in S3/S4, and off in S5. Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25google/cyan: Increase RO coreboot size on flashMatt DeVillier
Commit 05627831826cab096789bd19f004b33a4cd70c0e applied this change to other Google boards, but cyan was left out. Bring cyan in line with other Google boards. Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-25google/cyan: Remove support for pre-EVT boardMatt DeVillier
Cleaning up code to remove support for pre-EVT rev of cyan board. Analogous to what was done for intel/strago in commit 103f00d. Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Use GpioInt for Keyboard IRQJagadish Krishnamoorthy
Cherry-pick from Chromium commit a162348. Remove the hard coded IRQ number for the keyboard interrupt. IRQ number can change based upon the gpio bank index ordering. Hence pass the gpio bank and index number so that kernel calculates the IRQ number. Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable L1 sub stateT.H. Lin
Adapted from Chromium commit dc59188. Disable L1 sub state to prevent WiFi randomly disappear condition. Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 7f0cdf0. Cyan board add 4G DDR3L 2nd source memory (Micro/Samsung) Original-Change-Id: I12f82082d8227e61a97ce0a001d7d2b1f6613e06 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 3b578ef. Cyan board use new 2nd source memory (Micro/Samsung) Original-Change-Id: I6f4e8438faede7ac742776a622c265922e498898 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Fix Touchscreen InterruptJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1138727. Elan touchscreen driver expects the first gpio resource in asl to be the reset line. The driver considers the gpio based irq line as reset gpio resource and changes the direction to output. This will cause irq registration to fail. Solution is to pass Interrupt resource for touchscreen irq instead of GpioInt. Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Enable CA MirrorShobhit Srivastava
Cherry-pick from Chromium commit e49deb1. Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is board specific. Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1940eb6. The unused lines leads to spurious interrupts on few of the systems. Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Tested-by: Bernie Thompson <bhthompson@chromium.org> Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Clean-up the devicetreeRavi Sarawadi
Cherry-pick from Chromium 2b51633. Disable unused PCI devices. Update PCI DeviceID. Original-Change-Id: I34fa6e25f9178de959aad30cc979d787cf76b8ad Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Support reading Memory strap GPIOs to select SPDSubrata Banik
Cherry-pick from Chromium commit 8f63720. SoC GPIO to read Memory strap not getting configured correctly causing incorrect RAMID read during ROMSTAGE TEST=Build and boot the platform with differnt Memory type and read RAMID correctly inside spd.c RAMID = 0 => 4GB Samsung Memory RAMID = 1 => 4GB Hynix Memory RAMID = 2 => 2GB Samsung Memory RAMID = 3 => 2GB Hynix Memory Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-25mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetreePratik Prajapati
Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 09:58:15 +0000