Age | Commit message (Collapse) | Author |
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Stumpy is a Chromebox without a built-in display, and now
that default_brightness_levels.asl is no longer required
for all boards in a platform, drop it and the default panel
definition.
Test: build/boot stumpy
Change-Id: Iaf475f3529dd19330ea46532e9ffd20b44893f7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I588617bad4f4e9213021fb30cb6085273a36e70e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib89ffc86d84550971b2c9a437581f1ad8e5c04ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I22515873a28333607ad2552c1a417e649cfbaac8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ia380dd3faaaf7bdb16c8c877f5488dbbf01a4146
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ia5985bd013f68f5510dcad1de5a233f899a63ca0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I7b7670bb541cf4814fd4958d5c0d8c68cbee80c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I5aeaaf267a187105f08f48a010323baa77e06989
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ic2989038a5f11981682443e77d8f639a3ef280f5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I42ab3846c75adca1fe74dfa5114c9b697127bb76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1135a495053b1c1229c94c794664b23f50d50362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I90691355cfc73f0834d45024a2885998b5652f88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I9528563399d8f47570a602a378583487f3cacc8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8da7a1a2ae85eb0a5a33c18f233228d81f6938f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I68d2a8ac6f201f3c1131252b2b53b2b17ece1db6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib697a4b1eb74cced9f22c3c602215f0dcac81f20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I6537288b326172d70aac7849b8d9e33c7f5aff9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I840a776c237a630c0ff6df7d2ee065be51224658
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8fb7bc8056bbd940a2286b6a11a819335aa77ace
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Idcf639102b041ae46952df28c69dce02e1d3d689
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I2aa745e03e62ff8b9b5c9cb6f91d7f832f599f8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8c9d06fd4d369ae18447dadf6ca9107e7bdbc727
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ie43c93c371073b4fe071b08522f351d0e20ed561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I4d37fabe34265166019cdbbbe4ccb9772b87bff8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Iaabbc58a7089b28ebe23df3a04464234ff465486
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Iab4fb613bd33bc29630126a487525087c0fe7177
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I957a5e19c5ce39203e4afb94cbcb3d2961fdfb43
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ic93a89a2d5cbae851a3ed0d1f04055a182bbb85b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I32c5f5e865b5455ddb7034612ecea1383932cef9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I311c62e8321afa43fdb442e10158973ecdcca793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Id24c3a4fa195ccaafeb1932482c17562213505a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Test: build/boot lulu and samus variants, verify backlight
control functional under Windows 10.
Change-Id: I4725fdea5206ae03df14a8b07e51fdf09f1edebd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable SoC serial output by default, since no production devices
have this exposed, but leave it as a user option so it can be selected
as needed (eg, for use with a Google debug servo).
Same change as made for google/cyan in CB:39872
Change-Id: Id6b2c28658aca03d8c5042d719a0f6f504c29288
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The jack detect GPIOs are initialized as dual edge-triggered GPIs,
and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or
ActiveBoth -- a single interrupt is detected on jack insertion or
removal.
The Windows drivers on the other hand, will not function unless the
codec and LPE ACPI interrupts entries are set as in the Intel
Cherry Trail Tianocore platform reference code.
So adjust the ACPI interrupt triggers to make Windows happy, since
Linux doesn't care either way.
Test: boot Linux (GalliumOS 3.1) and Windows 10 on google/edgar,
observe functional audio output for both built-in speakers and
headphones.
Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/24989
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust CID to allow for Realtek's Windows drivers to attach
without breaking functionality under Linux.
Both Linux and Windows use ACPI HID/CID matching for driver attachment.
Since the Realtek 5650 isn't used in standard Windows laptops, the
'10EC5650' HID/CID isn't contained in the Windows drivers' lookup file
(.inf), but a catch-all 'INTCCFFD' entry does exist, so concatenate
that to the existing CID to allow the drivers to attach.
Test: build/boot google/edgar, verify working audio under
both Windows 10 (with Realtek drivers 10.0.10586.4393) and Linux
(GalliumOS 3.1 / kernel 4.16.18, Manjaro 18.1 / kernel 5.1.x)
Change-Id: Idca5cc86ba1f5ef3978cfba291a0c06e56ef5958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40003
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Braswell boards don't work well with the eMMC and SD controller
in ACPI in payloads other than depthcharge - SeaBIOS requires
an onerous workaround (manually determining the PCI BAR0 address
for each eMMC and SD controller, then adding adding etc/sdcard
entries to the CBFS), and Tianocore can't see the devices at all.
To make the common use-case work better, switch to PCI mode.
Test: build/boot cyan variants with SeaBIOS and Tianocore
payloads, verify eMMC and SD card visible and bootable to
both payloads and OSes.
Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40002
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simply cyan variants by converting to overridetree format.
A few differences were ignored as there appears to be no
reason behind them:
- cyan had PCIe RP2 enabled, but nothing is attached to it
- kefka had the SPI 1 device disabled
- reks, relm, and ultima had HSUART 1 disabled
- edgar had I2C1 UPD disabled
Test: build/boot cyan and edgar variants, verify everything
still works
Change-Id: I9928cc59adcfda4661ddfdfa95f53a7820053b4a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simplify glados variants by converting to overridetree format.
Change-Id: I6dd7a4b1ae7f1d3ce9fadb06ea95e021a1c880a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39983
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The VR config values used in the variants' devicetrees is
identical to the domain defaults in vr_config.c, with the
exception of the icc_max value, which is calculated dynamically
based on SKU, and again matches the default values for
each domain and each varaint.
Test: add a print function to dump the VR config values for each
domain from the UPDs after setting, verify same output before/after.
Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation for conversion to overridetree format, clean up
the variant devicetrees in order to minimize the differences
across glados variants. This entails:
- minor reformatting and reordering of devicetree entries
- addition of setting default values on boards which skipped them
- disabling unused I2C2 on boards which left it enabled
- ensuring TCC offset set for all SKL-Y boards
- setting VR mailbox command 1 for caroline
- skipping init for UART2 on cave and glados
- dropping unused PCIe RP5 for sentry
Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
As part of the cleanup, drop unused PCIe RP5 for buddy as well.
Test: build all auron variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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beltino variants are Chromeboxes without built-in displays,
so now that default_brightness_levels.asl is no longer required
for all boards in a platform, drop it.
Change-Id: Ie8147763fc9fdf4f184d3d000bffd6794e134d9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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No longer needed anywhere.
Change-Id: Ifeea76af44377d917ec46cac0d9d7375d1a68204
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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NDID/DID entries are no longer used by the GMA SSDT generator, so
drop them. SSDT generation will be simplified in a subsequent commit.
Remove direct setting of gnvs->ndid in qemu-q35 board since build
will otherwise break.
Change-Id: Ifbf08f43291c1fff7ccbc85272dc97334207983b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39954
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This commit creates a malefor variant for Volteer. The initial settings
override the baseboard was copied from variant ripto. Fine tune GPIO
and memory DQ based on malefor schematics.
BUG=b:150653745
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: Idbeebb13e537287686344740211143df35b7863a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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