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2017-11-30mb/google/poppy/variants/nautilus: Disable DPTFFurquan Shaikh
This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mainboard/google/fizz: Disable DPTF active policyDavid Wu
Use EC to perform FAN control. BUG=b:67487721,b:69404739,b:64439568 BRANCH=master TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: I3394d3af9cbdb3eab1f18254909f60e2704735c3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mainboard/compulab: add support for CompuLab Intense-PCHal Martin
Add coreboot support for CompuLab Intense-PC (Ivy Bridge) Modifications: - Memory SPDs have been fixed to detect both installed SODIMM modules - Full-height Mini-PCIe slot defaults to PCIe mode - mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA Tested (Xubuntu 17.10/Linux 4.13 where applicable): - 2+2GB DDR3-1600 SODIMMs pass memtest - 4+4GB DDR3-1600 SODIMMs pass memtest - 4+8GB DDR3-1333 SODIMMs pass memtest - 8+8GB DDR3-1333 SODIMMs pass memtest - Booting via USB working (with no SATA HDD present) - Booting to main SATA HDD working - DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS) - DisplayPort and HDMI dual-head working in Linux - Mini-PCIe devices (half/full-height) detected in Linux - mSATA working (when chosen using ENABLE_MSATA) - Onboard Intel 82579 GbE working - Secondary Realtek 8111 GbE working - Rear eSATA ports working - Onboard analog audio output working - HDMI audio output working - USB 3.0 working - Suspend to RAM (S3) working, but not tested extensively - Mini PCIe WiFi - FACE module FM-4USB (4 USB 2.0 ports) Disabled/unsupported: - TPM (BTO option, not included in base config) - FACE modules: - FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED - FM-SER (serial) NOT SUPPORTED/TESTED - FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED - FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED - FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED - FM-VC (video capture) NOT SUPPORTED/TESTED - FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED Not tested: - RS-232 Product information: http://www.fit-pc.com/web/products/intense-pc/ Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-30intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-30mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeCSubrata Banik
PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30mb/google/nautilus: add synaptics touch screen supportChris Wang
Add synaptics touchscreen in the device tree so that the correct ACPI device is created. BUG=b:66462881 BRANCH=master TEST=compiled/verify the touchscreen works Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-29google/kahlee: Add SPD functionMarc Jones
Add the mainboard_spd_read function in romstage and call the variants function. Grunt is the baseboard and has soldered down memory, so add it for the default weak SPD functions and build the SPDs in cbfs. Kahlee overrides the weak SPD function and falls back to the soc I2C SPD functions. BUG=b:67845441 TEST=Build and boot Kahlee. Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29google/kahlee: Rename board_id to memory_skuMarc Jones
The GPIOs used in board_id are meant to indicate the memory configuration. Rename board_id to memory_skus. Report the board_id received from the EC. BUG=b:69649438 Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22561 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29mb/google/poppy/variants/nautilus: Disable camera devicesFurquan Shaikh
This change disables camera devices until camera support is properly added for nautilus. Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29mb/google/poppy: Add variant support for camera aslFurquan Shaikh
This change adds infrastructure to allow variants to define their own camera.asl file. - Poppy and soraka use the one provided by baseboard. - Dummy file is added for nautilus since it does not have camera support enabled yet. TEST=Verified that DSDT table remains the same with and without this change. Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28google/scarlet: support kd097d04 panelLin Huang
Support kd097d04 dual mipi panel on Scarlet. Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28google/gru: correct backlight gpioLin Huang
it uses backlight enable pin as backlight gpio currently, correct it and define the right backlight gpio. Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: support dual mipi dsiLin Huang
Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang
Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settingsChris Wang
Change IA/GT/SA slow slew rate settings. System's audible noise will be reduced with them. - Slow slew rate for IA/GT/SA : fast/16 - Fast PKG C-state ramp for IA/GT/SA: disabled BRANCH=master BUG=none TEST=compiled/verified Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_tableDivya Chellap
On shutdown, Soraka enters Deep S5 and not S5 state. Setting pad reset config of a gpio to RSMRST will not preserve the gpio config across deepSx and the gpio should be configured again. The WLAN_PE_RST signal should be brought up early in the bootflow for giving the device enough time to initialized before PCIE init in FSP-S. Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in early pad configuration in bootblock also. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-28mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typoChris Wang
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mb/google/poppy/variants/nautilus: remove ALS for nautilusChris Wang
nautilus doesn't support ALS. remove the definition from ec.h. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Ib357328799015f78b18cd260db221e524e98cef7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mainboard/google/kahlee: Update Grunt for 16MB ROM chipMartin Roth
- Update Grunt to 16MB chip in Kconfig. - Move chromeos.fmd into variant directory & update Kconfig with the new location. - Add Grunt specific chromeos.fmd file. BUG=b:69691210 TEST=Build grunt; Build & Boot Kahlee Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28mainboard/google/kahlee: Update chromeos.fmdMartin Roth
- Remove SI_ALL section. This is no longer needed as the PSP dirctory is placed into the RO coreboot section. - Add 1MB Legacy section. - Add Memory cache section. These sections are called "MRC", which is an Intel term, but AMD platforms will use the same regions for saving the same sort of data. BUG=b:65497959, b:67035984 TEST=Build & boot kahlee Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-27google/fizz: correct memory rcomp settingsKane Chen
Follow the schematic and Doc 573387 to correct the rcomp and rcomp target settings for fizz TEST= boot ok and the system can enter and resume from S3. Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Remove tpm i2c configs from KconfigShelley Chen
We are disabling tpm over i2c, so the configs are not needed anymore. BUG=b:65056998 BRANCH=None TEST=emerge fizz and make sure can still boot up. Change-Id: Id88f32fa952801749544534442fc15d85fc1a892 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Disable unused i2c linesShelley Chen
As cr50 has now switched to using SPI, no need to enable the i2c1 anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and I2C3. BUG=b:69374421 BRANCH=None TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many) reboots. cat /proc/interrupts. Make sure # interrupts for 16 after booting is reasonable (not > 10k) and idma64.0, i2c_designware.0 are not listed with that interrupt line anymore. Should look something like this: 16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23google mainboards: select SYSTEM_TYPE_LAPTOP where appropriateMatt DeVillier
Some Google boards are missing this selection, leading them to being incorrectly identified as type 'Desktop' in SMBIOS type 3 table. Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards' Kconfigs. TEST: boot Linux and check correct chassis type listed via dmidecode Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23sb/intel/i82801ix: fetch initial timestamp in bootblockArthur Heymans
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23google/fizz: Define smbios_mainboard_sku to return OEM IDsShelley Chen
Currently, mosys just returns "fizz" as model/chassis values. Returning proper OEM IDs so that mosys can return the proper variant. BUG=b:67732053 BRANCH=None TEST=mosys platform model; mosys platform chassis; Make sure returns the right variant string and not fizz. Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22google/gru: Add support for rainierEge Mihmanli
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using GRU_BASEBOARD_SCARLET is enough, except for display related logic. In those cases, use board specific logic instead of baseboard. Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/22542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20mainboard/google/fizz: Enable separate MRC cache for recovery modeShelley Chen
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20google/gru: Add config for scarlet-derived boardsEge Mihmanli
There is merit in having new boards use the pinouts and controls in scarlet. This adds a config so new scarlet-derived boards can easily use scarlet structure without going through every file and adding new logic. TEST=Run "emerge-scarlet coreboot" Signed-off-by: egemih@chromium.org Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3 Reviewed-on: https://review.coreboot.org/22517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-17amd/gardenia: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21854 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelistKevin Keijzer
TESTED on Lenovo T500 Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17mb/lenovo/t400: Add LTN154X3-L02 to list of known displaysKevin Keijzer
TESTED on Lenovo T500 Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22475 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-15variants/kahlee: Add thermal ASLMarc Jones
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15google/kahlee: Get power plug notification from the ECMarc Jones
Set the EC SCI reporting mask to include the power plug reporting. BUG=b:65637324 TEST=Check power_supply_info on AC/DC. Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-14mb/google/eve: Add DSP calibration clock name/rate for RT5514Cheng-Yi Chiang
Add a property for DSP calibration clock name and rate such that RT5514 codec driver can control ssp1_mclk for DSP clock calibration. BUG=b:67763576 TEST=boot on eve check RT5514 codec driver can get this device property. Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31 Original-Reviewed-on: https://chromium-review.googlesource.com/756261 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Set DSP SPI clock to 12MHzDuncan Laurie
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable VMXDuncan Laurie
This feature was enabled at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. Since we want this enabled anyway just set it this way in the BIOS so it matches what the kernel expects. BUG=b:68666100 TEST=pass firmware_FWtries on Eve with R63 OS image Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/749733 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Tune I2C4 hold timesDuncan Laurie
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz. BUG=b:67029862 TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/739841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable AER and LTRFurquan Shaikh
AER and LTR must be enabled individually on ports that need it, in this case it should be enabled for WiFi and NVMe. BUG=b:65457528 TEST=Wifi team verified that the performance is better with these changes. Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/671211 Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 03:50:22 +0000