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2018-04-19mb/google/octopus: Select DRIVERS_I2C_HIDFurquan Shaikh
This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18mb/google/kahlee/variants/kahlee/gpio.c: Convert GPIO to new formatRichard Spiegel
As part of preparing to make GPIO code independent of vendor code references, convert GPIO table format using newly defined macros. BUG=b:77999987 TEST=Build and boot kahlee. Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-18mb/google/poppy/variants: Set VmxEnable to 1Furquan Shaikh
This change sets VmxEnable to 1 to match the kernel setting. If this feature is enabled at the kernel level and not in FSP, then there is an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. BUG=b:78129261 BRANCH=poppy Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25698 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17mainboard/google/kahlee: Add EC back into grunt devicetreeMartin Roth
The EC code should not have been removed from devicetree when moving over from grunt. This was causing various bewildering issues that would happen on the first boot but not on subsequent reboots. BUG=b:73235377 TEST=Grunt powers off and stays powered off at dev screen. Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-04-17mainboard/google/kahlee: Update EC pins from GPIOs to GPEsMartin Roth
The EC pin definitions are GPEs, not the GPIO numbers. BUG=b:74022675 TEST=Power status updates immediately when power is inserted. Change-Id: Icc8330a606f7a85e72b65094462a684927986829 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25689 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17mb/google/poppy/variants/nami: Update GPIOsShelley Chen
Updating some GPIOs based on changes in the latest schematics. Also renaming signals to match that of latest schematics. BUG=b:73749640 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Make sure different SKUs still boot. Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17mb/google/octopus: Enable Yorp EC software syncJustin TerAvest
With one additional EC change, Yorp is able to flash the EC as part of software sync and successfully boot. This change is only made for Yorp as we want this disabled for Bip bringup. BRANCH=none BUG=b:77874283 TEST=Successful flash and boot on Yorp with this change TEST=Checked GBB flags on Yorp and Bip images with gbb_utility CQ-DEPEND=CL:1014397 Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17cbfs: Add cbfs_boot_load_file()T Michael Turney
Generalize cbfs_boot_load_struct() by passing in CBFS type Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-17mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parametersFrank Wu
The commit enables DPTF function. The DPTF parameters are provided by thermal team. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot then check the parameters in DPTF ui tool Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/octopus: Add Write Protect GPIO to cros_gpiosHannah Williams
This will enable crossystem to access WP GPIO BUG=b:78009842 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15). BUG=b:77893710 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14). BUG=b:77930401 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16google/kahlee: Resume on AC insertionMarshall Dawson
The EC should wake the system from S3 when the AC connector is plugged. BUG=b:77602394 TEST=verify resume on insert with Grunt Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART muxAkshu Agrawal
bt-pad-enable property is used by kernel driver to set BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which use these pins for BT I2S. By default the pins are set for UART. BUG=b:72360151 TEST=Tested playback and capture on audio device connected to BT I2S Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25653 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16Revert "mb/google/reef/sand: Override USB2 phy settings"Katherine Hsieh
This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13src/mainboard/kahlee: Turn on keyboard backlight on gruntMartin Roth
Turn on keyboard backlight in romstage to indicate that the system is booting. BUG=b:77921345 TEST=Boot grunt, keyboard backlight comes on. Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13siemens/mc_apl1: Fix accuracy issue with IDT PMICMario Scheithauer
Due to an accuracy issue on IMON in the IDT PMIC, the reported system power consumption was higher than the actual consumption. To prevent this problem, a logic must be implemented in mainboard_init(). This logic consists of slope and offset as constants for Vcc and Vnn, which need to be programmed by coreboot. This fix compensates for the accuracy issue. Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-13Revert "mb/google/reef: Override USB2 phy settings"Tim Chen
This reverts commit 70ba1b7e78930acca578114cdadcbcec367730e8. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25630 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/google/kahlee: Fix IRQ routingRichard Spiegel
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to the NB Interrupt Routing Registers. The AGESA settings are: Device self INTA INTB INTC INTD GPP 0 23 0 1 2 3 GPP 1 24 8 9 10 11 GPP 2 25 16 17 18 19 GPP 3 26 24 25 26 27 GPP 4 23 3 0 1 2 HDA none 22 23 20 21 GBIF none 6 7 4 5 Fix the routing table, considering that NB IOAPIC starts at interrupt 24. BUG=b:74104946 TEST=Build and boot to a modified grunt board to enable the emmc. Then used "cat /proc/interrupts" to get active interrupts. Also checked IOAPIC redirection registers, which are now being programmed. Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13Revert "mb/google/coral: add usb2 phy setting override for some variants"Tim Chen
This reverts commit 06e3e1f055593bd2e2906f43040a703bc471cde4. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25629 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/scaleway/tagada: Document what the selected SMBIOS enclosure type meansJonathan Neuschäfer
This makes the Kconfig file more informative to read. Change-Id: Icdf4184c8db9cfed4863d9e9f3b714d67f44a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-12mb/google/octopus: Configure SMI for ESPIShaunak Saha
This patch enables EC SMI when ESPI is enabled. BUG=b:77857802 TEST= SMI is working in depthcharge. Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/google/octopus: enable MRC recovery cacheAaron Durbin
Enable the recovery cache to speed up recovery flows. Also enable clearing of the normal mrc cache on recovery forced retrains. BUG=b:77871444 TEST=went into recovery twice. 2nd time it boots faster. Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-11mb/google/octopus: Select DRIVERS_SPI_ACPIFurquan Shaikh
This change selects DRIVERS_SPI_ACPI which is required to add SSDT node for SPI TPM. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0728062dae017522ba91a4b5cb16acf9f6bf4f28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mainboard/intel/cannonlake_rvp: include correct SND related DT entriesSathyanarayana Nujella
For cannonlake_rvp, want to support two sound configurations based on relevant daughter board connected (either of these configurations: SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT). By default SSDT included all codec entries. This patch corrects and includes relevant codec entries in SSDT BUG=None BRANCH=master TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully. Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/24918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11siemens/mc_apl1: Make DRAM configuration more flexibleMario Scheithauer
By storing the FSP-M DRAM configuration parameter in the hwinfo block, one becomes more flexible in case of a change of the DRAM type. The configuration data from hwinfo block is a one-to-one representation of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and ending before parameter 'Ch0_Bit_swizzling' (offset 0x88). Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-11mainboard/google/kahlee: Enable Keyboard backlight for GruntMartin Roth
Grunt supports a keyboard backlight, so enable the ASL code. BUG=b:77455525 Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT. Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25470 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/intel/dg43gt/devicetree.cb: Use tabs over spacesElyes HAOUAS
Change-Id: I5d18dfea0b0a33995de805219bda3a73892e5fde Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-10mb/google/octopus: Capitalize MB part nameJustin TerAvest
This is for consistency with other platforms. BUG=b:77494826 BRANCH=None TEST=Sucessfully rebooted, saw updated name in SMBIOS Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25591 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mainboard: Make OemCustomize.c available at romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25528 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/poppy/atlas: Fix SPD index in commentJonathan Neuschäfer
Fixes: ba49c09b2f ("mb/google/poppy: Add variant for Atlas") Change-Id: I9c5c10abf8129ff61b97312a70ed4749606a3090 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/poppy: Disable rear camera for all vayne skuAmanda Huang
Since there are two cameras on Nami and only one camera on Vayne. We need to disable rear camera on all Vayne sku. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera shown on Vayne Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-09mb/google/octopus: Enable EC wakeShaunak Saha
This patch sets the wake for EC to proper gpios. BUG=77605178 TEST=Test that lidopen wakes up the system from S3. Change-Id: Icbf30007403191005396027e74b9b6fb7319e006 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25539 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus/variants/baseboard: Add DPTF parametersSumeet Pawnikar
This patch adds the DPTF parameters for Octopus baseboard. These parameters are copied from reef/coral as initial reference values. BUG=None BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621 Reviewed-on: https://review.coreboot.org/25339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-06mb/lenovo/w520: Add ThinkPad W520 supportNico Rikken
Tested and working: * 4 RAM-slots * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events * USB 3.0 * SD-card reader * Native graphics (LCD panel) * Harddisk in Ultrabay * SeaBIOS payloads ** Debian Live ** Debian testing 4.14.0-3-amd64 * GRUB ** Debian Live ** Debian testing 4.14.0-3-amd64 Not working: * Displayport and VGA output (requires VGA option ROM and ACPI switch call) Not tested: * Intel VGA option ROM * ACPI events related to ultrabay * Smart card reader * Docking station Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/23564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-06mainboard: Add ASUS Maximus IV GENE-ZTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with kernel 4.9. This code is based on the output of autoport. Working: - S3 suspend/resume - USB - Gigabit Ethernet - integrated graphics - PCIe - SATA - eSATA - PS/2 port (only a mouse has been tested) - hardware monitor - onboard audio - front panel audio - native raminit (2 x 4GB + 2 x 8GB, DDR3-1333) - native graphics init with libgfxinit - EHCI debug. The debug port is the port closest to the HDMI port. - flashrom, using the internal programmer. Tested with coreboot, untested with the vendor firmware. - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been tested with values different from the default. Untested: - VGA BIOS for graphics init - PCIe graphics - S/PDIF audio Not working: - "clear CMOS" button The CPUTIN sensor on the Super I/O is not connected. The PECI agent is likely connected instead to give CPU temperature readings. However, there does not appear to be enough information in the publicly available datasheets to fully set up the PECI agent. As a result, there is currently no accurate, automatic fan control via the Super I/O. Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/24971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel ECNaresh G Solanki
When building with Intel EC selected, unselect Chrome EC specific options i.e., LID switch to prevent build error. BUG=None BRANCH=None TEST=Build with Intel EC selected, Build should be successful. Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25479 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/google/octopus: Edge trigger cr50 interruptJustin TerAvest
Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/google/octopus/variants/baseboard: Enable DPTF supportSumeet Pawnikar
This patch enables DPTF support for Octopus baseboard. BUG=None BRANCH=None TEST=None Change-Id: I88a94c73ef0c9da708c0440f7edadd85488edfdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-06purism/librem_skl: Add AC/DC LoadLine to VR ConfigYouness Alaoui
The FSP 2.0 needs to set the ac_loadline and dc_loadline for each VR config. Without it, the Loadline is considered to be 0 mOhm and this causes CPU temp to jump all over the place whenever the CPU is used. This is necessary since there are no VR_CONFIG icc mappings for Skylake SKUs, only KabyLake. These values were copied from the Google Poppy devicetree. Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06purism/librem_skl: Set TCC Activation at 95CYouness Alaoui
Set the Thermal Control Circuit (TCC) activaction value to 95C even though FSP integration guide says to set it to 100C for SKL-U (offset at 0), because when the TCC activates at 100C, the CPU will have already shut itself down from overheating protection. This was tested on Purism Librem 13 v2. A bisect showed that the immediate shutdowns happened after commit [1] was merged which led to this solution. [1] ec5a947b (soc/intel/skylake: make tcc_offset take effect) Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06purism/librem_skl: Enable VMX and Intel SpeedStep in devicetreeYouness Alaoui
Although VmxEnable is currently ignored by FSP, a forthcoming patch explicitly enables it in coreboot, so set it in anticipation of that. Enable Intel SpeedStep to ensure the ACPI tables are generated for the C-states/P-states which are required for the xen-acpi-processor module to be loaded. Without it, the Qubes 4.0-rc4 installer will complain at boot about modules that could not be loaded. Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06purism/librem_skl: Enable TPM supportYouness Alaoui
Change the GPIO to match the TPM-enabled motherboards, and add TPM support in devicetree and enable the config. After changing the GPIO table, the librem 13v2 and librem 15v3 now have the same GPIOs, so use a single gpio.h file instead of one file per variant. Change-Id: I425654c1c972118aa81c27961246238c2eef782d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/23683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-04-05mb/amd/gardenia/gpio.c: Convert GPIO to new formatRichard Spiegel
New macros were developed that replace previous way of defining GPIO, with pin and intention very clear while keeping the table mostly identical to previous method (there's no pull up or pull down when a GPIO is set as an output). Change current gardenia table to use the new macros. BUG=b:72875858 TEST=Build Gardenia. Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05mainboard/google/kahlee: Update WP to active lowMartin Roth
The WP signal to the AP isn't inverted as it is on other platforms, so it was reporting incorrectly. Change the ACPI table to be active low, and invert the signal when reporting it to everything else. BUG=b:74946358 TEST=Boot grunt with battery inserted, WP signals both report 1. Remove battery, WP_CUR reports 0, WP_BOOT still reports 1. Change-Id: Ic1369dbda609e34b308af308880449643be6af39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-04mb/google/octopus/variants/baseboard: Set PL1 and PL2 valueSumeet Pawnikar
This patch sets PL1 value to ~6W. Here, 8W setting gives a run-time 6W actual measured power. Also, this patch sets PL2 value to 15W. BUG=None BRANCH=None TEST=Build and read the MSR 0x610. Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 15:16:23 +0000