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2017-05-19mainboard/lenovo/t430: Add Thinkpad T430 supportPhilipp Deppenwiese
Tested and working: * HDD LED * Booting GNU Linux 4.9 from HDD using SeaBios * Booting GNU Linux 4.9 from USB using SeaBios * Native GFX init * All Fn function keys * Speakers * PCIe Wifi * Camera * WWAN * Fan (Dynamic Thermal Managment) * Flashing using internal programmer * Dual memory DIMMs running at up to DDR3-1866 * AC events * Touchpad, trackball and keyboard * USB3 ports running at SuperSpeed * Ethernet * Headphone jack * Speaker mute * Microphone mute * Volume keys * Fingerprint sensor * Lid switch * Thinklight * TPM (disable SeaBios CONFIG_TCGBIOS) * CMOS options: ** power_on_after_fail ** reboot_counter ** boot_option ** gfx_uma_size ** usb_always_on Untested: * Booting Windows * Hybrid graphics * Docking station * VGA Broken: * Wifi LED is always on Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-19mb/lenovo/t400: Generate undock event with dock buttonArthur Heymans
Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-18google/scarlet: Enable innolux,p079zca MIPI panelNickey Yang
TEST=Boot from scarlet, and mipi panel works Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-17siemens/mc_apl1: Program eMMC DLL settingsMario Scheithauer
Program eMMC DLL settings for mc_apl1 mainboard, after that system can boot up with eMMC successfully. Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-17siemens/mc_apl1: Select external 8250 UARTMario Scheithauer
The mainboard siemens/mc_apl1 uses an external I/O port for console output. For this reason we need to activate the 8250 LPC UART. Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17mb/google/eve: Remove FPC device from SPI1Duncan Laurie
This device is no longer directly connected to the SOC so it does not need to be enabled in coreboot. BUG=b:35648259 TEST=build and boot on Eve Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19728 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mb/google/eve: Update touchpad I2C timingDuncan Laurie
The touchpad frequency was still slightly above 400kHz so tweak the timing values manually to get under the spec limit. BUG=b:35583133 TEST=verified the bus frequency with a scope to be < 400kHz Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19727 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mainboard/google/poppy/variants/soraka: Enable H1 I2C TPMFurquan Shaikh
1. Add a separate devicetree file for soraka variant and add H1 node. 2. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19519 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17mainboard/google/poppy: Correct I2C bus number for TPMFurquan Shaikh
TPM is on I2C bus 1. Fix that. BUG=b:36265511 Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19710 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17google/fizz: Configure SATAXPCIe GPIOs to use native functionShelley Chen
BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-05-15vexpress: change to write32Vladimir Serbinenko
Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/19685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-13vexpress: add gfx initVladimir Serbinenko
Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-13mainboard: Add ASRock G41C-GSArthur Heymans
Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-12mb/gigabyte/ga-g41m-es2l: Don't disable PATAArthur Heymans
This board features a PATA port. TESTED PATA drive works in SeaBIOS and OS. Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-12mainboard/google/reef: Config needed GPIO for pull-up WALijian Zhao
This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-12qemu/vexpress-a9: Discover RAM size.Vladimir Serbinenko
Probe RAM to find its size instead of hardcoding 1024M. Also properly export it to memory map. Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-11mainboard/pcengines/apu2: Add LPC TPM supportPhilipp Deppenwiese
APU2 exposes a LPC header which can be used in conjunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-11mb/sapphire/pureplatinumh61: Sanitize KconfigNico Huber
Remove overrides that set platform defaults or insane values. Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2017-05-11siemens/mc_apl1: Add usage of external RTC RX6110 SAMario Scheithauer
This mainboard contains an external RTC chip RX6110 SA. Enable usage of this chip and set some initialization values to device tree. Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-11mb/lenovo/x60/t60: Remove `fn_ctrl_swap` optionNico Huber
The EC doesn't support it. Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-11mb/lenovo/x201: Add support for ThinkLightStefan Ott
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the ThinkLight from the Operating System. This patch adds partial support for that method, enough to enable or disable the ThinkLight: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light With the original BIOS the UCMS method exposes a wide range of values through a generic /proc/acpi/ibm/cmos interface. With the changes suggested in this patch that interface is also exposed but only accepts the commands to enable or disable the ThinkLight; all other commands are ignored. This change would potentially benefit all currently supported Thinkpad models, I only have an X201 available for tests though. Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/19644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-11nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
Currently only one board uses this northbridge in coreboot but some patches are pending to add more. Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11nb/intel/gm45: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11nb/intel/i945: Define and use a default MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11siemens/mc_apl1: Correct GPIO settingsMario Scheithauer
- set GPIO_183 to high level for enabling the power of SD card - delete all GPIOs for JTAG interface because they lead to problems with Lauterbach debug hardware Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-11google/gru: support 800M/928M frequency for bobCaesar Wang
The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-11rockchip/rk3399: enable DPLL SSC for DDR EMI test on bobCaesar Wang
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-10mb/lenovo/s230u: fix sata port map for the msata portpersmule
s230u seems only have two sata ports: one for the 2.5in hdd and one for msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5 (port 0 & 2) enables both. Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-05-09mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socketBill XIE
Tested against a lenovo-manufactured tpm 1.2 module: a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards. Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19521 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-09superio/ite/it8728f: Hook up common environment-controller driverTobias Diedrich
This replaces the custom environment controller handling in the it8728 driver with the common library. It also updates the two existing boards with hwm register settings in their devicetree config so they better match their vendor BIOS fan control settings. Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/19293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-05-09google/sand: Add keyboard backlight supportKatherine Hsieh
BUG=None TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08mainboard/intel/galileo: Add SD controller configurationLee Leahy
Configure the SD controller to handle the SD card slot. * Galileo supports a removable SD card slot. * Set SD card initialization frequency to 100 MHz. * Set default removable delays. * Build SD/MMC components by default TEST=Build and run on Galileo Gen2 Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-08mb/google/reef: enable SAR and DSARWei-Ning Huang
Enable SAR and DSAR for reef. BUG=b:37612675 TEST=`emerge-reef coreboot` Change-Id: Ie0a59f8fcc9fb104328ee6d276ecab4193ec8eb8 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/19579 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05mb/google/poppy: Add eMMC as thermal sensorSumeet Pawnikar
This patch adds the eMMC as one of the thermal sensor under DPTF. Also, updates few comments for better interpretation and mapping. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/19524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-05Revert "google/scarlet: Enable innolux,p079zca MIPI panel"Martin Roth
This reverts commit 39b633b26d6d4cf185fbbdd5a256d0665409bd5b. Commit was accidentally pushed too early and broke the tree. I'll repush the original. Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-05google/scarlet: Enable innolux,p079zca MIPI panelNickey Yang
TEST=Boot from scarlet, and mipi panel work Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-05mainboard/google/sand: Update DPTF parameters provided from thermal teamKatherine Hsieh
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:83, critial point:99 TSR0 passive point:60, critial point:70 TSR1 passive point:50, critial point:90 TSR2 passive point:77, critial point:90 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 4W, max to 12W, and step size to 0.2W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 5secs Change CPU Effect on Temp Sensor 0 sample rate to 60secs The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs Change Charger Effect on Temp Sensor 2 sample rate to 30secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=None TEST=build and boot on electro dut Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05google/fizz: Enable devices under pci 1c.0Shelley Chen
Turn on device 1c.0 in order to enable devices under it. BUG=b:37486021, b:35775024 BRANCH=None TEST=Boot from NVMe Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19533 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-05mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASKFurquan Shaikh
This is required to ensure that SCI is generated whenever a host event is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs, eSPI SCI is generated which results in kernel handler reading host event from the EC and thus causes the wake pin to be de-asserted. BUG=b:37223093 TEST=Verified that wake from mode change event works fine in suspend mode and there is no interrupt storm for GPE SCI after resume. Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jenny Tc <jenny.tc@intel.com>
2017-05-05mainboard/siemens/mc_apl1: remove unnecessary headerAaron Durbin
soc/i2c.h does not need to be included in this compilation unit. Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-04mb/gigabyte/ga-b75m-d3h: add libgfxinit supportpersmule
Currently native video init works on port HDMI1 (wired to the on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA port, both text mode and fb mode. Every ports works on GNU/Linux. Tested against an IVB cpu (i7-3770T). Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/19522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-04mb/lenovo/x200: Make button on dock to undock workArthur Heymans
Fetched from vendor DSDT. Change-Id: Ib74408802e977d9caabcb815c9cbd06bd8dbe395 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kevin Keijzer <kevin@librepractice.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-05-04mb/google/eve: Remove code to set keyboard backlight at bootDuncan Laurie
Remove the code that was enabling the keyboard backlight at boot since this is not desired behavior for this device. BUG=b:35581264 TEST=build and boot on Eve and ensure keyboard backlight does not turn on when booting but can still be enabled in the OS. Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-04mb/google/eve: Set SUSWARN# pin to native functionDuncan Laurie
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied to SUSACK# in the schematic and and is intented to be used in Deep Sx so it should not be configured for GPIO mode. BUG=b:35581264 TEST=build and boot on Eve platform, test that Deep S3 and Deep S5 are still functional. (this change should have no visible effect) Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03google/gru: skip usbphy1 setup for Scarletphilipchen
Board Scarlet doesn't use usbphy1. BUG=b:37685249 TEST=boot Scarlet, check the firmware log, and confirm no errors about USB1 Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-03nb/intel/gm45: Set display backlight according to EDID stringArthur Heymans
Add some known good values for some thinkpads displays. Known good means that at this pwm frequency the display is evenly lit on all duty cycles, the display makes minimal to no noise at lower duty cycles and the display does not flicker. This values differs from vendor (which uses an obviously wrong display clock (190MHz instead of 320MHz) resulting in frequency more than 60% off the intended value. TESTED on Thinkpad X200 with edid ascii string in list and removed from list to see if notice message is shown. Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Update GPIO table for next buildFurquan Shaikh
Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-01mb/*/mainboard.c: Get rid of SPI AFC registerPatrick Rudolph
The AFC—Additional Flash Control Register is set by southbridge code. Remove redundant calls and get rid of it in autoport. Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19493 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 12:53:40 +0000