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2014-05-06rambi: include the EC devices normally on superioAaron Durbin
The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: update EC supportAaron Durbin
Fix the SMI and SCI gpios for Rambi. Also, add in the EC callbacks for the SMI handler. Note that the handler for GPI SMIs has not been tested yet as baytrail chipset code doesn't yet support setting up those configurations yet. BUG=chrome-os-partner:23505 BRANCH=None TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts for the EC's SCI GPI. Also was able to see Chrome EC messages with CONFIG_DEBUG_SMI and powering down at the dev screen. Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176077 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4948 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06baytrail: configure acpi SCI irqAaron Durbin
Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4946 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mirror bayleybay's eMMC gpio setupAaron Durbin
These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: Fix eDP panel functionalityDuncan Laurie
For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4944 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM StringTrevor Mosey
linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC version string before loading, this code copies the vendor BIOS by exposing this string. This was originally part of x60's mainboard.c Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845 Signed-off-by: Trevor Mosey <uberushaximus@gmail.com> Reviewed-on: http://review.coreboot.org/5638 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05baytrail: fix up FADTAaron Durbin
The FADT for baytrail had incorrect offsets leading to the kernel spewing a huge mess of ACPI errors. Fix these offsets to be initialized in the chipset code. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted into kernel on rambi. Login screen comes up. Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175663 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4941 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05baytrail: interrupt routing supportAaron Durbin
This provides the initial support for interrupt routing in bay trail. It includes both acpi changes and board changes to ensure the interdependencies are met with the current ASL code. The PIRQ routing is handled by the mainboard exporting an irqroute.h header that describes the per device and PIRQ PCI settings. There are still a lot of ACPI errors in the kernel with this change, though. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted rambi into kernel. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e Reviewed-on: https://chromium-review.googlesource.com/175700 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Fix BiosCallouts table formattingKyösti Mälkki
Already done for fam15tn and fam16kb. Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Use common calloutsKyösti Mälkki
Backported from fam15tn and fam16kb. This also implements GetHeapBase() to satisfy some requirements of HAVE_ACPI_RESUME for the following boards: amd/inagua amd/south_station amd/union_station asrock/e350m1 Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5658 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Add fam14_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5657 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05jetway/nf81-t56n-lf: Revert change on function prototypesKyösti Mälkki
These function prototypes to remain identical across all AGESA families. Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add GetHeapBase()Kyösti Mälkki
While fam15 boards do not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add GetHeapBase()Kyösti Mälkki
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam16kb: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Use common calloutsKyösti Mälkki
Backport from fam15tn and fam16kb. Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add fam15_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Move dimmSpdKyösti Mälkki
Implemented under northbridge/ on other families. Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add fam12_calloutsKyösti Mälkki
Although amd/torpedo is only fam12 board at the moment, backported this from fam15tn and fam16kb. Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AMD F14h boards: Sanitise headers in agesawrapper.cEdward O'Callaghan
Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5628 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05AMD F14h boards: Use std memset/memcpy func over AGESAEdward O'Callaghan
In amd/{persimmon,inagua} and derived boards avoid using AGESA reimplementation of memcpy as following the reasoning in: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA Change-Id: I943b46103c3bf1c5fd88b25e9f9595b9adfcafeb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5625 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05lenovo/t60: Move mainboard_enable() code into a mainboard_init()Trevor Mosey
mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: I89a5192bd45ca8321b2b1ac49b073122e0f6ee2b Signed-off-by: Trevor Mosey <uberushaximus@gmail.com> Reviewed-on: http://review.coreboot.org/5637 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Drop useless mainboard-romstage definesPatrick Georgi
Some src/mainboard/*/*/romstage.c files use defines which later modify the behaviour of included .c files. Since it's a pain to work out what is affected by these, drop values that are only defined in the board but never used, or defined to identical values as in spd.h (and use that one instead). Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5639 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02qemu-armv7: Kconfig cleanupKyösti Mälkki
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7. Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1: Sanitize #includesEdward O'Callaghan
Following similar reasons as: 5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2014-05-02jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptablesEdward O'Callaghan
Jetway builds this hardware, so let us be sure to set the truth in the DSDT Definition block and MPTables. Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1/devicetree.cb: Correctly indent device linePaul Menzel
Fix up commit dfa8a32f [1]. src/mainboard/asrock/e350m1: Properly indent devicetree.cb [1] http://review.coreboot.org/5612 Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5619 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cbEdward O'Callaghan
Following the reasoning in, dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5629 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02mainboard/*: Use generic winbond romstage in place of w83627thgEdward O'Callaghan
Use the generic implementation of winbond in place of the model specific w83627thg_enable_serial() as so that it maybe removed later. Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5603 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01ChromeOS: Use common fill_lb_gpio()Kyösti Mälkki
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01ChromeOS: Remove oprom_is_loadedKyösti Mälkki
A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01google/stout: Fix build without ChromeOSKyösti Mälkki
Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30baytrail: Clean up NVS regionDuncan Laurie
There is a lot of NVS allocated to things that are not really used. Most of these are removed and some are moved around. Thermals are expected to be handled with DPTF so I've removed that bit of code but have not yet cleaned up the thermal zone. I left in the SIO BARs since I think we will need those still even though they may need work still. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Id16ee67e6b3709a303c001afd72947147f938127 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175626 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4936 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add reserved MMIO regions to ACPIDuncan Laurie
Add a length define for all the reserved MMIO regions and use them in the ACPI code to reserve the regions there. Add a region for the "abort page" documented in the EDS. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175624 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4934 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Fix XHCI problems and re-enableDuncan Laurie
- a few clock gating bits were set improperly and were preventing the system from transitioning out of S0 state. - the XHCC registers were not getting the top byte set properly which includes things like DMA write request size and request boundary crossing control. This was causing memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot kernel from USB on rambi with XHCI driver Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4933 Tested-by: build bot (Jenkins)
2014-04-30mainboard/: Avoid including early_serial.c from w83627hfEdward O'Callaghan
Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5597 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30console: Move UART port defaults to mainboardKyösti Mälkki
Correct selection of UART depends of board layout, not the CPU internals, so default setting should originate from mainboard. Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5618 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30console: Drop EARLY_CONSOLE optionKyösti Mälkki
We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5607 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30uart: Support multiple portsKyösti Mälkki
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in commentPaul Menzel
$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g' Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5325 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29src/mainboard/asrock/e350m1: Properly indent devicetree.cbEdward O'Callaghan
Trivial: clean up spaces to tabs to properly indent devicetree.cb Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5612 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29mainboard/kontron/986lcd-m: Remove a duplicate headerEdward O'Callaghan
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5602 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-28superio/winbond/w83627ehg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28mainboard/tyan/s8226: Remove redundant sio headerEdward O'Callaghan
Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627dhg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28mainboard/asrock/e350m1: Avoid including early_serial.cEdward O'Callaghan
Use generic winbond romstage serial init symbols instead of model specific implementation. We do this on a case by case basis as some boards are ROMCC and so need to #include .c files. This is a step to migrate non-romcc boards to a more generic superio framework. Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5591 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 22:55:21 +0000