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2016-05-03mainboard/intel/galileo: Enable I2C and GPIOLee Leahy
Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14558 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01mb/emulation/*/board_info.txt: Update QEMU URLJonathan Neuschäfer
Change-Id: If4d57c7898c0de20035533dccd4554f45a71d5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14525 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-29soc/intel/apollolake: clarify Fast SPI CS2 pad configurationAaron Durbin
The pad for CS2 of the Fast SPI interface needs to be configured for automatic MMIO translation when a SPI TPM is utilized. Instead of unconditionally configuring that pad under LPC_TPM provide a explicit Kconfig for a mainboard to select. Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/14531 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-04-29siemens/mc_bdx1: Add new mainboard.Werner Zeh
Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which does not match any standard. This commit adds the new mainboard and prepares the Kconfig environment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14516 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-04-28Add board URLs for the RISC-V boardsJonathan Neuschäfer
Change-Id: Ifdf40986c2407d8c5b0097654b42e056f4498d39 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14518 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-28Fix "Spike RISCV" board nameJonathan Neuschäfer
Change-Id: If0f835e69862a78433e7c1a34efa4706cc27b214 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14517 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-28drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh
Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28mc_tcu3: Switch to hwilib instead of own hwinfo implementationWerner Zeh
Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch does not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14506 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28mainboard/amenia: Enable Chrome EC Interface/KeyboardDivya Sasidharan
Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28soc/intel/apollolake: Configure a GPIO for TPM in bootblockAndrey Petrov
One of devices connected to FAST SPI bus is TPM. SoC uses dedicated line for chip select for TPM function. If TPM is used, that line needs to be configured to a specific native funciton. Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-26mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stageTimothy Pearson
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel. Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS. Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21mainboard/apple: add license headersNoah Glovsky
Change-Id: Id9487212411e5c237d26eb4e5663135f7d0720d1 Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org> Reviewed-on: https://review.coreboot.org/14425 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21mainboard/amd: add license headersNoah Glovsky
Change-Id: Ida8e81c88b2016d90cc8305edfb199143f859ec2 Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org> Reviewed-on: https://review.coreboot.org/14422 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-20mainboard/amenia: add the inital files for amenia boardZhao, Lijian
Add amenia board files Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20AMD CIMX: Drop unused codeKyösti Mälkki
We never define B1_IMAGE or B2_IMAGE. These are about building CIMx as separate binary modules, while coreboot builds these into same romstage or ramstage module. Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20mb/lenovo/x220: disable MEAlexander Couzens
The ME hangs, the lspci shows no memory and the linux kernel tries to request irq 0 twice. After suspend-resume the linux kernel warns about double used irq. genirq: Flags mismatch irq 0. 00000080 (mei_me) vs. 00015a00 (timer) mei_me 0000:00:16.0: request_threaded_irq failed: irq = 0. dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -16 PM: Device 0000:00:16.0 failed to resume async: error -16 Change-Id: I56ef66388e58dddcfb858294ba274621c55fbef6 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14309 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-16mainboard/google/gru: Add license header to memlayout.ldMartin Roth
I missed this license header, and it's causing a build breakage. Change-Id: If472e5c081bd282f0b482af629d6ec2314a2c329 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14388 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2016-04-16google/gru: Incorporate feedback to #14279Patrick Georgi
To avoid diverging too much on an actively developed code base, keep the changes to a separate commit that can be downstreamed more easily: - removed unused includes - gave kevin board a "Kevin" part number - marked RW_LEGACY as CBFS region (to follow up upstream changes) - moved romstage entry point to SoC code (instead of encouraging per-board copy pasta) Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-16google/gru: Add a stub rk3399 mainboardhuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. [pg: separated out from the combined commit that added both SoC and board. Added board_info.txt that will be added downstream, too.] Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/14279 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-15mainboard/intel: Add Broadwell-DE based Camelback Mountain CRBYork Yang
Initial files to support Camelback Mountain CRB. This board uses Broadwell-DE code which is based on FSP 1.0. Change is based on Broadwell-DE Gold release. Windows 7 and Fedora 21 have been verified using SeaBIOS payload, also Fedora 21 with U-Boot payload. Change-Id: Ie249588b79430084adeebbcdd8b483d936c655e3 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14015 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-04-14mb/asus/kgpe-d16|kcma-d8: Do not assign IRQ to LPC HW monitorTimothy Pearson
On specific revisions of the ASUS KGPE-D16 (> 1.03G) there is a high (< 1:10) chance of lockup from spurious HW monitor IRQs during LPC configuration. This was originally erroneously identified as a bug within the SP5100 southbridge due to serial console buffering moving the hang slightly before HW monitor setup. It is currently unknown how changing the CBFS layout / code size was able to alter the frequency of the lockup occuring; this odd characteristic made debugging extremely difficult, and it also indicates testing across multiple PCB revisions will be neded to verify that the bug has been completely resolved. It is highly likely that the KCMA-D8 is also affected. As there does not seem to be a reason to keep the HW monitor IRQ enabled, simply disable it on both mainboards. This configuration has passed burn-on power cycle testing with no lockups noted. All other tests noted a lockup in under 25 power cycles or so, with failure typically occuring in under 5 power cycles; the affected Rev. 1.04 KGPE-D16 has cycled 25 times times using this patch with only one failure finally noted. This final failure may have in fact been related to SP5100 Erratum 18 as the frequency is more in line with the errata document guidelines. Change-Id: Ie9f4f37d2c7dfad0a02daff8b75cd2a1e6f1b09a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14333 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14intel/apollolake_rvp: Add sleepstates.asl to dsdtHannah Williams
cat /sys/power/state should show supported sleep states as freeze and mem where freeze is "Suspend to Idle" and mem is "Suspend to RAM" Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14285 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14mainboard/intel/apollolake_rvp: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Ia78cf5a4b283b846346e5e50c6b2b36299a6a892 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14363 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13lenovo/t420: Add new portNicolas Reinecke
This is based on t420s. Tested on a T420 without discrete GPU. There is no support for nvidia gpu and optimus. Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: Iru Cai <mytbk920423@gmail.com> Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8 Reviewed-on: https://review.coreboot.org/11765 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13mainboard/google: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13mainboard/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14322 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13soc/intel/apollolake: Enable TPM in bootblock stageBora Guvendik
Configure gpio FST_SPI_CS2_N before verstage so that tpm can be accessed. Change-Id: I238bf1cd508880b686f0625f28175a80de450971 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-10beaglebone: Add code to set the value of the LEDsGabe Black
The LEDs on the beaglebone are connected to GPIOs called USR0-USR3. This change adds some functions to make it easy to set their value and clear what the calling code is trying to do. Change-Id: I0bb83bbc2e195ce1a0104afcd120089efaa22916 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: https://review.coreboot.org/3943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-10mb/samsung/lumpy/romstage: read SPD data of removable DIMMPatrick Rudolph
The removable DIMM SPD data wasn't read. As a result the system only uses the 2GB onboard memory and the GNU Linux kernel paniced in acpi_ds_build_internal_package_obj. Read the SPD and allow native raminit and MRC blob to use the removable DIMM. The system is able to use the removable dimm and the kernel panic is gone. Change-Id: I30eed747f924cb0029de55d2ab85c5a94075dc1b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/14278 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08mb/asus/kgpe-d16|kcma-d8: Enable early MCE reportingTimothy Pearson
Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14266 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-07mainboard/intel/apollolake_rvp: Include FADT tablesLance Zhao
Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13353 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-06src/mainboard: Disable power_on_after_fail CMOS option for laptopsPhilipp Deppenwiese
power_on_after_fail=Enable in cmos.default leads to wake on AC behaviour on mobile systems. Therefore set cmos.default entry to "Disable" in order to improve user experience. Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/13884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-04-05mb/asus/kgpe-d16|kcma-d8: Add ehci_async_data_cache CMOS optionTimothy Pearson
Change-Id: I76a1047742369416b90e5c8bf307f85c02ae9bbb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14242 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-05chromeos.fmd: Mark RW_LEGACY as CBFSPatrick Georgi
Change the existing chromeos.fmd files and the dts-to-fmd script to mark RW_LEGACY as CBFS, so it's properly "formatted". BUG=chromium:595715 BRANCH=none TEST=none Change-Id: I76de26032ea8da0c7755a76a01e7bea9cfaebe23 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 717a00c459906fa87f61314ea4541c31b50539f4 Original-Change-Id: I4b037b60d10be3da824c6baecabfd244eec2cdac Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/336403 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14240 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05google/oak: Log hardware watchdog in eventlogJulius Werner
The MT8173 hardware watchdog can assert an external signal which we use to reset the TPM on Oak. Therefore we do not need to do the same double-reset dance as on other Chromebooks to ensure that we reset in a correct state. Still, we have a situation where we need to reconfigure the watchdog early in the bootblock in a way that will clear information about the previous reboot from the status register, and we need that information later in ramstage to log the right event. Let's reuse the same watchdog tombstone mechanism from other boards, except that we don't perform a second reset and the tombstone is simply used to communicate between bootblock and ramstage within the same boot. BRANCH=None BUG=None TEST=Run 'mem w 0x10007004 0x8' on Oak, observe how it reboots and how 'mosys eventlog list' shows a hardware watchdog reboot event afterwards. Change-Id: I1ade018eba652af91814fdaec233b9920f2df01f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07af37e11499e86e730f7581862e8f0d67a04218 Original-Change-Id: I0b9c6b83b20d6e1362d650ac2ee49fff45b29767 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334449 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14234 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-04-05google/chell: Adjust nuvoton 8825 button thresholds again.Benson Leung
Changing these thresholds again for new tuning in March of 2016. Something's changed in the latest firmware to cause all values previously read on Chell to float down. Set "nuvoton,sar-threshold" property to thresholds based on tuning with the Android Wired Headphone Compatibility Kit and Chell DVT. Signed-off-by: Benson Leung <bleung@chromium.org> BUG=chrome-os-partner:49333 BRANCH=none TEST=Run evtest, selecting the input event for sklnau8825adi Using the Nominal headphones from the kit, check that the buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA", and code 582 (?) (should be voice search, but evtest doesn't understand) All of these buttons should work properly. Change-Id: Ie5ff1d35599d2cca5ce76467ecd7ec3ecab42d8b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d13e967addb5cd31e6196e32541cda97ae00257 Original-Change-Id: I11de7a0853a3598f3834e8bae3140b9942cbd0b0 Original-Reviewed-on: https://chromium-review.googlesource.com/334402 Original-Commit-Ready: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14233 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05chromeos: Simplify fill_lb_gpios even furtherJulius Werner
A long time ago many Chrome OS boards had pages full of duplicated boilerplate code for the fill_lb_gpios() function, and we spent a lot of time bikeshedding a proper solution that passes a table of lb_gpio structs which can be concisely written with a static struct initializer in http://crosreview.com/234648. Unfortunately we never really finished that patch and in the mean time a different solution using the fill_lb_gpio() helper got standardized onto most boards. Still, that solution is not quite as clean and concise as the one we had already designed, and it also wasn't applied consistently to all recent boards (causing more boards with bad code to get added afterwards). This patch switches all boards newer than Link to the better solution and also adds some nicer debug output for the GPIOs while I'm there. If more boards need to be converted from fill_lb_gpio() to this model later (e.g. from a branch), it's quite easy to do with: s/fill_lb_gpio(gpio++,\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\));/\t{\1, \2, \4, \3},/ Based on a patch by Furquan Shaikh <furquan@google.com>. BUG=None BRANCH=None TEST=Booted on Oak. Ran abuild -x. Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14226 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-04-04mainboard/emulation/qemu-power8: Use correct bootblock locationTimothy Pearson
Change-Id: Ia1e8f7c11708208638f83dc1058f1754e69d4d0c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14020 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-03-30storm: Fix compilation errorFurquan Shaikh
Somehow the missing header file in https://review.coreboot.org/#/c/14182 did not trigger compilation errors before. Add the required header file to enable proper compilation of storm. Change-Id: I83c8f2b5fc41e38c1385ff405370753e6eba2abc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14185 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-29google/chell: Update DPTF thermal parametersDuncan Laurie
MinPL1: 2.5W MaxPL1: 7W StepPL1: 0.25W _PSV(TSR2): 51C _TRT(TSR2): 9 second BUG=chrome-os-partner:49859 BRANCH=glados TEST=build and boot on chell Change-Id: I69de1d66fb0d52ad0ad77eb51ca56f50fc44c255 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 845f1d046a5143057d683b2bd9cf5dab2ab2ef34 Original-Change-Id: I8a161c979a22621f5f854926677cb7835f8ce88b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332857 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-(cherry picked from commit 4d5023524591fc6b651a199874ed990bd5be1d50) Original-Reviewed-on: https://chromium-review.googlesource.com/333071 Reviewed-on: https://review.coreboot.org/14119 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-29intel/kunimitsu: configure native mode for GPP_E21Youvedeep Singh
GPP_E_21_DDPC_CTRLDATA is pulled low by default. This causes 2.5mW leakage from 3.3S to GND via R877. So configuring GPP_E21 in native mode. BUG=chrome-os-partner:50958 BRANCH=glados TEST=Build and boot. Measure Power at 3P3S(R955). Change-Id: I2bdcb698d0b0cd3228c2e59653ac3fb3b1a26951 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d01f932cda44b0b44c5494b316aefc43c8b84c52 Original-Change-Id: Ifd13ea4b16108ef98d09891365f0d17831ab5f65 Original-Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332369 Original-Commit-Ready: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14108 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-29ipq806x/storm: Return NULL for cbmem_top if DRAM is not initializedFurquan Shaikh
DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-25google/intel mainboards: Add missing board_info.txt filesMartin Roth
The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14117 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-21soc/apollolake: Add skeleton ACPI entryLance Zhao
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-21nb/intel/sandybridge: increase MMCONF_BASE_ADDRESSPatrick Rudolph
Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. The sandybridge chipset code assumes 64 pci buses behind MMCONF. Therefore, only 64MiB of physical address space is required. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible to use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-03-21google/oak: Move external buck initialization to coreboothenryc.chen
Remove the code which is passing parameters to ARMTF and move external buck initilizaton from ARMTF to coreboot. BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I4f4b30acbee9b42a202b326f2fe4517cb4b9d83c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37bec54b4d8a3bce38878e292e4821da3959026a Original-Change-Id: Ib81709812a064f6daf13c9b4d6525f1858c81393 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332343 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mainboard/intel/galileo: Enable SPI controllersLee Leahy
Enable the SPI controllers on the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when the time is able to be displayed on a set of seven-segment displays controlled by a Maxim MAX6950 SPI display controller. Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18google/oak: Enable RAM_CODE_SUPPORTYidi Lin
BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 12:36:07 +0000