summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2017-10-28mainboard/google/Kahlee: Combine BiosCallOuts filesMartin Roth
There's no need to have these separated. BUG=b:64932381 Test=Build & Boot Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26purism/librem_skl: add new variant Librem 15 v3Matt DeVillier
Add new board librem15v3 as a variant of the librem_skl baseboard. Changes from the librem13v2: - Change board name and version - Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO - Enable PCI device 1c.4 - Change USB port definitions in devicetree TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22048 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-26purism/librem13v2: convert to variant setupMatt DeVillier
Convert the Purism Librem13v2 board to a variant setup, in preparation of adding the librem15v3 as a new variant. The 13v2 and 15v3 are nearly identical, so this minimizes new code to add support for the latter. Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22047 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-24mainboard/intel/cannonlake_rvp: Enable variant gpio configurationJohn Zhao
This patch refers to variant_gpio_table for board gpio configuration. Change-Id: If5b4c20ceccb32fc1ab4246482d8fecb491777c4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-10-23mb/sapphire/pureplatinumh61: Remove S3 resume delayNicola Corna
It seems that recent changes in coreboot have fixed the raminit issues on this board; the workaround of 10 ms delay after the S3 resume is not needed anymore and can be removed. Change-Id: If8fb97ecf3eb797f53270a053201fafd32031678 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23purism/librem13v2: migrate from FSP 1.1 to 2.0Matt DeVillier
Migrate the Librem13v2 from using FSP 1.1 to the public/GitHub FSP 2.0 Skylake/Kabylake release: - select FSP 2.0 in Kconfig - adjust romstage/ramstage functions as required - refactor pei_data functions - remove VR_RING domain from devicetree (unsupported in FSP 2.0) - add SataSpeedLimit parameter to work around power-related issue when operating at SATA 6.0Gbps speed TEST: build/boot Librem13v2, observe successful boot, lack of SATA-related errors in dmesg. Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23mainboard/google/coral: Add USB2 phy setting override for Astronautren kuo
In order to pass type C USB2 eye diagram for sku Astronaut, USB2 port#1 PHY register needs to be overridden. sku ID:0,1 Astronaut (USB) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 sku ID:61,62 Astronaut (LTE) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 5 BUG=b:68120012 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Signed-off-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22superio/ite/common: Add temperature offsetVagiz Trakhanov
Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Update microcode length in CBFSYouness Alaoui
Microcode blob has been updated, so update the length to match Change-Id: I46ac10e5c6cd6492c98a7034649797f301101abc Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22purism/librem13v2: Fix USB settings and set OC pinYouness Alaoui
The USB settings were wrong in some places, or missing and the USB_OC values were taken from the schematics. Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Update devicetree settingsYouness Alaoui
Disable SataDevSlp and update other values to match vendor/AMI firmware. Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Change DRAM Rcomp/DQS valuesYouness Alaoui
The RComp values have been updated to match what is shown in the schematics. Extracting the Memory configuration blob from the original BIOS (A blob which contains the correct binary sequence matching the RComp values appears in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find and confirm the DQ and DQS mapping. Small code cleaning in romstage.c with no effect. Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22purism/librem13v2: Add reading of serial number from CBFSYouness Alaoui
Check CBFS for 'serial_number' field, and use value if exists; otherwise use value set at compile time. Change-Id: I4b50f6310ca32b9dd372db075a5b5729e3b06619 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22google/kahlee: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22amd/gardenia: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: I44c7df6a2be149ed61094f67ef1c578736e5b55c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22mb/google/link: Enable libgfxinitNico Huber
Beside the high-resolution eDP panel, it features a dual-mode mini-DP port. Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-20kahlee: Set Kahlee GPEsMarc Jones
Add GPE configuration table. Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22). Set the EC and PCIE/WLAN SCI GPIO signals. Set GPE ASL methods for: PCIE/WLAN 8h EHCI 18h XHCI 1fh Note EC GPE3 methods are in the EC ASL. BUG=b:63268311 BRANCH=none TEST=Test lidswitch powers the device on and off at the login screen. Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22096 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20google/fizz: Set PL2 value based on sku id/charge max powerShelley Chen
Set PL2 based on either 90% of usb c charger's max power or sku id if using a barrel jack. BUG=b:37473486 BRANCH=None TEST=output debug info for different skus and make sure PL2 set correctly. Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20stoneyridge: Fix USB ASLMarc Jones
Stoney Ridge has one EHCI controller and one XHCI controller. Also, update the Kahlee and Gardenia mainboards ASL to match. Change-Id: I5749ca0640796732e74e551147f8c4446317b77e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20intel/cannonlake_rvp: Update board nameLijian Zhao
Change the board name from cannonlake U DDR4 to U LPDDR4 to match actual platform. TEST=NONE Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20soc/intel/cannonlake: Add platform.aslLijian Zhao
Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20Stoney Ridge Platforms: cast AGESA tables to void *Martin Roth
In the original AGESA headers, these tables are not defined as const. Cast them to void * so that they'll work with either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22059 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20Stoney Ridge Platforms: Make AGESA callout tables commonMartin Roth
There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. Move chip specific functions into the stoneyridge directory: - agesa_fch_initreset - agesa_fch_initenv - agesa_ReadSpd Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which to use. Soldered-down memory still needs to be supported in a future commit, as stoney supports both DDR3 & DDR4. A bug has been filed for support for the upcoming Grunt platform. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-20mainboard/pcengines/apu2: add apu3 and apu5 variantsKamil Wcislo
Apu3 and apu5 are additional variants of apu2 board. Apu3 has no LPC connector exposed, but has additional USB header. It has also 2 slots for SIM cards and one of the gpios is used to control switching between them. Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches). This patch adds support for those other variants by not introducing additional code redundancy. Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Reviewed-on: https://review.coreboot.org/21981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-19siemens/mc_bdx1: Initialize GPIOsWerner Zeh
Add GPIO initialization for mc_bdx1 mainboard. Call init_gpios() as early as possible as FSP will set up things (like hiding PCI devices) rather early. If connections on the mainboard are dependent on GPIO settings then FSP can screw things up (e.g. disabling not yet connected PCI root ports). Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19AGESA f14: Fix DDI maps in OemCustomize.cKyösti Mälkki
Creates identical object files. Change-Id: Ie8adb21a753cee6a72dae5eeb64a255e6ead2fe7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19AGESA: Split long lines in OemCustomize.cKyösti Mälkki
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19AGESA f14: Drop PlatformGnbPcieComplex.hKyösti Mälkki
These were OEM configurations hidden inside a header file, notation was already dropped for f15tb and f16kb. Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19pcengines/apu2: Add timestamps to romstageMichał Żygowski
This change adds timestamps to romstage in order to keep PC Engines apu2 platform in active codebase. Change-Id: Ie0286d4982623da9d035c47df6077edaf51e5110 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/22071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19mb/google/poppy: Log EC events during S0ix resumeFurquan Shaikh
This change adds support for logging EC events during S0ix resume. BUG=b:67874513 TEST=Verified that EC events are correctly logged during S0ix resume: 284 | 2017-10-16 20:45:12 | S0ix Enter 285 | 2017-10-16 20:45:16 | S0ix Exit 286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0 287 | 2017-10-16 20:45:16 | EC Event | Power Button 288 | 2017-10-16 20:45:35 | S0ix Enter 289 | 2017-10-16 20:45:40 | S0ix Exit 290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112 291 | 2017-10-16 20:45:40 | EC Event | Lid Open 292 | 2017-10-16 20:50:51 | S0ix Enter 293 | 2017-10-16 20:50:59 | S0ix Exit 294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112 295 | 2017-10-16 20:50:59 | EC Event | Mode change Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18mainboard/intel/cannonlake_rvp: Enable hardware P state controlVaibhav Shankar
This patch provides configuration parameter to enable/disable Intel Speed Shift Technology. Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-18intel/cannonlake_rvp: Enable Audio DSPLijian Zhao
Enable Audio DSP by default on cannonlake rvp platform. TEST=Boot up into OS and check Audio driver debug print. Change-Id: I6892c6d349019550c967ef30b84d385f396fc388 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18intel/cannonlake_rvp: Declare PCIE clock usageLijian Zhao
Define PCI express clock usage for cannonlake u and cannonlake y rvp based on board design. TEST=Bootable into OS. Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18google/snappy: Override USB2 strength by SKUIDKevin Chiu
14" BigDaddy needs to override USB2 TxiSet additionally to enhance driving strength. Otherwise EA test will fail on USB2 eye pattern. BUG=b:67820719 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I674c121a71866a5d44439eeb49e07f917d816de8 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18mb/google/fizz: skip reading SPD data when DUT resumes from S3Gaggery Tsai
This patch skips SPD data reading when system resumes from S3 since MRC cahce is adopted and validated in fsp_memory_init. BUG=b:67021596 TEST=Run suspend/resume on Fizz and make sure the systems are working well when system resumes from S3. Checked dmidecode information and SMBIOS type 17 data is the same with cold boot. Change-Id: I1692fca8456290d1471973b746537b5fec504e03 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-17intel/cannonlake_rvp: enable HS400Bora Guvendik
Set SCS emmc HS400 enable FSP parameter. TEST=Boot to OS, verify HS400 SDHCI print Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22008 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-17amd/agesa: Remove redundant UDELAY_LAPIC selectionPaul Menzel
This is already selected in `src/cpu/amd/agesa/Kconfig`. Change-Id: I691a2ade10ee461b6bc34ea24d57a911281791f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16intel/cannonlake_rvp: Modify memory parameters to support LP4 boardLijian Zhao
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4 platform. TEST=Able to boot up on CNL U LPDDR RVP. Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16google/reef: Add more special cases for coral nasherPatrick Georgi
BUG=b:65386429 BRANCH=none TEST=panel lights up Change-Id: I9871969314b9b64bee2b20332e35bfc6fbd2ddda Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16src/mainboard/google/kahlee: Remove legacy tablesRichard Spiegel
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables. Use Kconfig for reversable configuration if using old OS. BUG=b:62241143 Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16mb/google/fizz: enable AER for PCIe root portsKane Chen
Enable PCIe Advanced Error Reporting for PCIe root port 2, 3, 4 ,8. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21946 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16mainboard/pcengines/apu2: use GENERIC_SPD_BINKamil Wcislo
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom. Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Reviewed-on: https://review.coreboot.org/21980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-16src/mainboard/kahlee: Default AMD FW position to 1MBMartin Roth
For Kahlee, the AMD firmware directory should be in the 1MB location so that it's in the RO cbfs section. BUG=b:65484600 TEST=Build & boot Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22003 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-15amd/inagua: Drop unused Broadcom 5785 support codeKyösti Mälkki
Remove sample configuration code for internal Broadcom GbE device in AMD A55E aka Hudson-E1. Change-Id: Ib0262805aafc62513d9237019ade473cb1efbf1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15google/kahlee: Add SMI sleep handlerMarshall Dawson
Notify the EC the system is going to sleep. Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/kahlee: Add SMI apmc handlerMarshall Dawson
Forward the apmc call to the chromeec. Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/wizpig: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/wizpig (white label Chromebook) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new wizpig variant - Add new shared SPD file to the baseboard Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15google/ultima: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/ultima (Lenovo Yoga 11e G3) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new ultima variant Sourced from Chromium branch firmware-ultima-7287.131.B, commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode"" Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-15google/setzer: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/setzer (HP Chromebook 11 G5) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new setzer variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 06:38:30 +0000