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The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The Asus F2A85-M, F2A85-M LE and F2A85-M PRO all have a Super I/O, and
therefore have legacy devices like a serial console.
Selecting `HUDSON_LEGACY_FREE` currently disable the serial console
during bootup in romstage, which is undesired.
So, deselect the symbol by default.
TEST=Boot Asus F2A85-M PRO and verify serial console is *not* disabled
during romstage.
Change-Id: Ia6588c0d4b2c24c7cb9da04805d13274c8ae295e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47363
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the shuboz variant of the zork reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172021093
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code is based on autoport, with necessary modifications.
This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.
Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.
Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Adds ACPI properties for WDT8762A device.
Per spec v0.8
HID name WDHT2002
T14=100ms
BUG=b:163561649
BRANCH=puff
TEST=emerge-puff coreboot and check system dmesg and evtest can get device.
Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Hook up PCH thermal subsystem configuration to devicetree.
Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The X86 Qemu targets use the AMD64 SMM save state, but unlike
most AMD CPU's the PM ACPI SMI port is not configurable and uses
the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch replaces if-else-if ladder with switch case for readability
purpose.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the genesis variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172620124
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_GENESIS
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.
Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct USB over-current mappings in devicetree now that the
GPIO config has been fixed per schematics.
Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The LAN NIC is onboard, not installed in a slot.
Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add strings for M.2 keying and number of PCIe lanes.
Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.
Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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- set pads GPP_B6/B8 for PCIe CLK_REQ lines
- set pad GPP_B14 to speaker output
- adjust comment for GPP_C22 / USB3_P1_PWREN
- set pad GPP_E4 to NF1 / SATA_DEVSLP0
- set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1#
Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47220
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add information regarding the privacy pin on the overridetree and the
gpio.
BUG=b:171888751
Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:169840271
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update Power Limit2 (PL2) minimum value to the same as maximum value
for magolor board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=b:168353037
BRANCH=None
TEST=Build and test on magolor board
Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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LTE module used in boten has a specific power on/off sequence.
GPIOs related to power sequnce are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: Power off -> 500ms -> Power on
Configure the GPIOs based on these requirements.
BUG=b:163100335
TEST=Build and boot Boten to OS. Ensure that the LTE module power
sequence requirements are met.
Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This support is required to power off certain components that exist only
in certain variants.
BUG=None
TEST=Build and boot Boten to OS.
Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.
Added memory
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:171755775
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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This patch makes Atlas resume from S0ix by AC plug and unplug.
BUG=b:165328935
BRANCH=atlas
TEST=Put Atlas in suspend. Wake it up by AC plug.
TEST=Put Atlas in suspend. Wake it up by AC unplug.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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EEPROM in the camera module does not require any specific power
resources. This will ensure that no unnecessary resources are turned on
while accessing the camera EEPROM.
BUG=b:167938257
TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is
listed in the output of i2cdetect.
Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Handle AC connect and disconnect notifications from Embedded Controller
(EC) and wake from S3/S0ix.
BUG=b:172266344
TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up
from suspend on AC connect and disconnect on both the TypeC ports.
276 | 2020-11-04 12:21:29 | S0ix Enter
277 | 2020-11-04 12:21:40 | S0ix Exit
278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected
279 | 2020-11-04 12:21:57 | S0ix Enter
280 | 2020-11-04 12:22:03 | S0ix Exit
281 | 2020-11-04 12:22:03 | EC Event | AC Connected
282 | 2020-11-04 12:22:35 | S0ix Enter
283 | 2020-11-04 12:22:47 | S0ix Exit
284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected
285 | 2020-11-04 12:23:08 | S0ix Enter
286 | 2020-11-04 12:23:16 | S0ix Exit
287 | 2020-11-04 12:23:16 | EC Event | AC Connected
Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
dedede variants (baseboard and drawcia). Currently, variants like boten,
waddledee, waddledoo, metaknight and wheelie uses the DTT entries from
baseboard devicetree since there is no override present for these variants.
So, these variants will also reflect this change of PL1 minimum value.
For madoo variant, PL2 minimum value already set the same as PL2 maximum
value. DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on drawcia system
Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board
Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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InternalGfx isn't used so drop it.
Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Config voema to use CSE LITE
BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Production Volteer devices have Cr50 TPM connected via SPI, depending on
Cr50 firmware version it may or may not support long enough interrupt
pulses for the SoC to safely be able to enable lowest power mode.
Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced
with Dauntless, communicating via I2C. The I2C drivers do not support
being accessed early in ramstage, before chip init and memory
mapping, (tlcl_lib_init() will halt with an error finding the I2C
controller base address.)
Since the Dauntless device under development can be made to support
longer interrupts, or a completely new interrupt signalling mode, there
is no need to try to go through the same discovery as is done via SPI.
This CL will skip the discovery, enabling the S0i3.4 sleep mode in all
cases, on the reworked test devices.
BUG=b:169526865, b:172509545
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x
Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current I2C3 bus frequency is 341 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C3 frequency is 394kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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This setting copy from puff reference board
and should measure again after whole system build.
BUG=b:155261464
BRANCH=puff
TEST=emerge-puff coreboot and check system speaker has sound output.
Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Use devicetree.cb from default location
2. Create variant directory for ADL RVP with external EC as
'adlrvp_p_ext_ec'
3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec'
to override 'devicetree.cb' as applicable.
4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec'
to mainboard directory
TEST=Build and boot both ADLRVP with onboard and external EC.
Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the xeon_sp pch.asl to include the intel common lpc.asl.
Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use the xeon_sp pch.asl to pickup the common block lpc.asl. This
allows deltalake to pick up any general pch asl updates. Currently,
generates the same asl.
Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47304
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The BMC isn't always ready in 60 seconds if it printing debug output.
Give it 90 seconds to finish before timing out in coreboot.
Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
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The patch configures GPIO pins to enable DMIC.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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The patch enables ALC711 Audio codec.
Test=Verified on ADL RVP.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers
for ADLRVP.
BUG=b:170607415
TEST=Built and booted on ADLRVP.
Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the HPD1 and HPD2 GPIO's.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the hotplug
functionality is working.
Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD
variables.
FSPM MemRefreshWatermark option support is present in FB's CPX-SP
FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP
FSP binary, this option takes the space of UnusedUpdSpace0[0].
For DeltaLake mainboard, if corresponding VPD variable is set, use it
to control the behavior. Such control is effective when FB's CPX-SP
FSP binary is used.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Adjust USB2 phy si setting fine tune on DVT for Ezkinil.
BRANCH=zork
BUG=b:156315391
TEST=Measuring scope timing and test usb detection
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set numerous pads to PAD_NC as per board schematics (they are either
NC, or connected to test pads), and adjust comments as needed.
Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Update gpio and devicetree for elemi.
BUG=b:170604353
TEST=emerge-volteer coreboot and boot into kernel
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Config elemi to use CSE LITE
BUG=b:170604353
TEST=emerge-volteer coreboot
Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:170604353
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add new SKU definition:
Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39
BUG=b:170708728
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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