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2020-07-23mb/prodrive/hermes: Update VBT fileChristian Walter
Update .vbt file to support two DP outputs. Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23ec/system76_ec: add support for System76 ECJeremy Soller
This adds ACPI code for System76 EC and converts system76/lemp9 to use EC_SYSTEM76_EC. Tested on system76/lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-23mb/ocp/deltalake: Add ipmi POST start command in romstageTimChu
Add function to send POST start command to BMC. This function is used in romstage and the POST end command will be sent in u-root. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1: ipmid: POST Start Event for Payload#2 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23mb/ocp/deltalake: Implement SMBIOS type 9 -- system slots by SKUMorgan Jang
Create SMBIOS type 9 by getting PCIe config from BMC. TEST=Check SMBIOS type 9 is created correctly on different SKUs Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVPKrishna Prasad Bhat
This patch enables CSE Lite SKU for jasperlake rvp. BUG=b:160201335 BRANCH=None TEST=Build and boot jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40571 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvpKrishna Prasad Bhat
This patch enables the SkipCpuReplacementCheck config for jasperlake rvp to avoid the forced MRC training with the soldered down SOC. BUG=b:160201335 BRANCH=None TEST=Build and verify on jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede: Enable the CSE Lite SKU for dededeV Sowmya
This patch enables the CSE Lite SKU for the dedede baseboard. BUG=b:160201335 TEST=Build and boot waddledoo with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23mb/google/dedede: Skip the CPU replacement check for dededeV Sowmya
This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddledoo. Cq-Depend: chrome-internal:3142530 Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-22mb/google/zork: Modify Woomax variantKane Chen
Update Woomax configuration including GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158343602 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-22mainboard/amd/mandolin: describe where the two HDA codecs resideFelix Held
Change-Id: I99b062e4ce1cf862ea03b0edb6ea843df5f8f2b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURETim Chu
Change PCH power policy. Set default of POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power state to S5 when power is reapplied after power failure. TEST=Base on CB:42289, CB:43338 and build for Deltalake. The following Kconfig options must be selected: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and check the last bit of GEN_PMCON_B is set to 1 through ITP with command: pch.pm_dump Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22mb/ocp/deltalake: Set FSP log level and add default values if VPD variables ↵Johnny Lin
are not found 1. Read VPD variable 'fsp_log_level' to decide FSP log level. 2. Define the default values when the VPD variables cannot be found, put all the values to vpd.h for better documentation and maintenance. Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable. Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22mb/google/kukui: revise config structure for Jacuzzi followersHung-Te Lin
There are more Jacuzzi followers coming and we want to have a simplified way of adding new boards. Now, detachable and tablets should select BOARD_GOOGLE_KUKUI_COMMON and clamshells should select BOARD_GOOGLE_JACUZZI_COMMON. BUG=None TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper BRANCH=kukui Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-21mb/google/dedede: Create madoo variantIan Feng
Create the madoo variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:161191394 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_MADOO Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-21mb/googlz/zork: Drop unnecessary PULL_UPs in variant overridesFurquan Shaikh
This change drops the pulls configured on override GPIOs as they already have external pull-ups. Also, pads which are unused are configured as PAD_NC. BUG=b:154351731 Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-21mb/system76/lemp9: drop FSP_M_XIPMichael Niewöhner
Drop FSP_M_XIP since it's selected by the soc already. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-07-21mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARYMichael Niewöhner
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards with multiple graphics devices. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21mb/lenovo/t430/gma-mainboard.ads: Replace with GPLv2+ equivalentPeter Lemenkov
Replace it with t430s/gma-mainboard.ads which is licensed under more flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I633702d363134654e71e35404237d75b499f089a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21mb/lenovo/t420/gma-mainboard.ads: Replace with GPLv2+ equivalentPeter Lemenkov
Replace it with t420s/gma-mainboard.ads which is licensed under more flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I5393a603b5a4cd353149c1fa9e3e29020946b962 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21mb/biostar: Add TH61-ITX portMate Kukri
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge) - RAM: native raminit tested (4G+4G, 8G+8G) - USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4) - LAN: tested in Linux - SATA: all 4 ports work, tested in SeaBIOS and Linux - iGPU: I can't test it as I only have a Xeon for this socket - PEG: tested with an nVidia GT210, initialized by SeaBIOS - PS2 keyboard and mouse combo port: no devices to test with - Front panel header: tested, works - Audio: tested, works - Diagnostic LEDs: TBD Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20google/trogdor: Remove write_protect_stateEric Lai
This is no longer used for chromeos.c. BUG=b:160752610 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a716a88ff9811fff46abca229be15522733bfef Reviewed-on: https://review.coreboot.org/c/coreboot/+/43472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20mb/google/dedede: Update link frequency and end point structure for OV9734Pandya, Varshit B
1. Update Link frequency to 180 Mhz 2. Set data-lanes to 1 and 3. Update the clock-lane used by sensor BUG=b:155285666 BRANCH=None TEST=Build and able to capture image using user facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20mb/amd/mandolin: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for dalboz referenceFurquan Shaikh
This change drops internal pulls for dalboz reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP1800_S0 GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_32: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for trembyle referenceFurquan Shaikh
This change drops internal pulls for trembyle reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP3300_A GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_90: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-20mb/asrock/b85m_pro4: Enable VGA portAngel Pons
Now that libgfxinit has been fixed, trying to enable the Analog port no longer hangs the system, nor fills the monitor with unreadable garbage. Tested with linear framebuffer, displays correctly on a 1920x1080 VGA monitor. Scaling also works when a smaller HDMI monitor is connected as well. Legacy VGA text mode is also functional on either monitor, too. Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19mb/qemu-i440fx/memmap: Add warning when falling back to CMOS infosNico Huber
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Fix return code check for fw_cfg_e820_select()Nico Huber
Change-Id: I22b9eb6ead37dbba6807d145468843bd01c94c84 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Add info messages about (not) found filesNico Huber
Print some more information at BIOS_INFO, like our CBFS code does. Change-Id: I1431d569c57634277ea5cf7feb352419db432b44 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43444 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/volteer: Update DPTF with temp sensor 3Tim Wawrzynczak
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those. BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-17mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine deviceFurquan Shaikh
Vilboz requires a different HID than rest of the zork variants. Hence, this change sets the HID to AMDI1015 for I2S machine device in vilboz overridetree.cb. BUG=b:157708581 Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Switch to using newly added i2s_machine_dev driverFurquan Shaikh
This change switches zork devices to use the newly added i2s_machine_dev driver in devicetree rather than passing dmic_select_gpio in SoC config. BUG=b:157708581 Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17mb/asrock/b85m_pro4: Select MAINBOARD_USES_IFD_GBE_REGIONAngel Pons
This board uses the in-PCH GbE controller, and its IFD has a GbE region. Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/amd/mandolin: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: correct wake gpe value for gpio 9Aaron Durbin
GPIO_9 is associated with gevent 22. Correct all the misconfigurations and use macros for clarity as to what bit offset is being used instead of open coding things. BUG=b:161205804 Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_ENFurquan Shaikh
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle boards using devicetree settings. BUG=b:161328042,b:146317284 Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUsFelix Held
Dali supports two SATA ports, but no PCIe alternate function on those pins. Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/amd/mandolin: fix DXIO lane numbersFelix Held
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/amd/mandolin/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/google/zork: Move variant_pcie_gpio_configure() to bootblockFurquan Shaikh
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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