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2019-12-19mb/{msi,pcengines}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I282d02d58a5740369371a6f0bbdf7e900e3edc56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src/mainboard/amd: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I61982309a4110f4f40193190e91224e909b575a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19mb/{asrock,asus}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I14d3579f232b1dcc95b4e0653520686965dbe727 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19mb/{cavium,opencellular,roda,scaleway,ti}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: Iad616e98feaebc6d5ec058fbf438ac2002a6b934 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33903 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19mb/{hp,intel}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: Ib6151ac245870a198afb71909a36a0840480d567 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19mb/{gizmosphere,google}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19mb/biostar: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I03d1af0858952972c92b83375a55dbda87e69f8a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src: Remove unneeded 'include <delay.h>'Elyes HAOUAS
Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34230 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19arch/x86: Drop uses of ROMCC_BOOTBLOCKArthur Heymans
Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-18src: Remove unused 'include <bootblock_common.h>'Elyes HAOUAS
Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37271 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17mb/emulation/qemu-q35: Drop unused romcc-related KconfigArthur Heymans
Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-17mb/msi/ms7721: Switch away from ROMCC_BOOTBLOCKElyes HAOUAS
Renze Nicolai tested it on hardware: boots into Linux without problems. Change-Id: I17e09c366ae0c9c99d5c65dd1f00672697a7c709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37737 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17mb/intel/icelake_rvp: Remove baseboard gpio configuration supportAamir Bohra
Remove baseboard gpio.c and rely on variant override. Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37512 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17src: Conditionally include TEVTFrans Hendriks
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized), which indicates the TEVT method is empty. The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT. The TEVT method will be removed from the ASL code when the EC does not support TEVT. BUG=N/A TEST=Tested on facebook monolith. Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-17src/mb/Kconfig: add BOARD_ROMSIZE_KB_5120Angel Pons
Mainboards exist with a 4+1 MiB flash chip combination. Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-17mb/google/rambi: add VBTs for variantsMatt DeVillier
Add VBTs for all rambi variants, extracted from VGA BIOS from stock firmware images using intelvbttool. Test: boot several rambi variants using MrChromebox edk2/master branch with Baytrail GOP driver and extracted VBTs. Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-17mb/google/jecht: Add VBTs for all variantsMatt DeVillier
Add VBTs for jecht variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except tidus, since it differs from the others. Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-16src/soc/intel/cannonlake: Bump MAX_CPU from 8->12Edward O'Callaghan
This impacts boards: hatch (&variants) and drallion. Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. Further to that, boards themseleves shouldn't be setting the MAX_CPUS, the chipset should be and so do that. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-16biostar/am1ml: Switch away from ROMCC_BOOTBLOCKSergej Ivanov
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c' TEST=Boots into Ubuntu Linux 16.04.6 without a problem. Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-16mb: Use fixed value in RcompTarget structureWim Vervoorn
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of the RcompTarget structure. All other structures in these functions use a fixed value. Replace RCOMP_TARGET_PARAMS with fixed value. BUG=N/A TEST=build Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/google/beltino: Add VBTs for all variantsMatt DeVillier
Add VBTs for beltino variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except monroe, since it differs as it has a built-in display (being a Chromebase vs Chromebox). Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16mb/google/slippy: Update VBT fileMatt DeVillier
Update VBT using file extracted from VGA BIOS from stock firmware image using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/google/auron: add VBTs for variantsMatt DeVillier
Add VBTs for all auron variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Test: boot several auron variants with libgfxinit and Tianocore payload, ensure both internal and external displays as well as HDMI audio function properly under Linux (4.x/5.x). Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16arch/x86: Make X86 stages select ARCH_X86Arthur Heymans
Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/facebook/monolith: Add vboot-ro.fmd to support measured bootWim Vervoorn
Add an fmd file with a layout that allows configuring the system for measured boot without enabling verified boot. BUG=N/A TEST=tested on facebook monolith Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/facebook/monolith: Remove % tag from fmd fileWim Vervoorn
cbfstool doesn't support % tag yet while this was in the fmd. Revert the fmd changes that use the % tag. BUG=N/A TEST=build Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16mb/facebook/monolith/gpio.h: Update GPIO configurationWim Vervoorn
Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16mb/g/drallion: Remove Wilco 1.0 CML variants from drallion codeMike Wiitala
Remove the sarien_cml and arcada_cml subdirectories from the drallion/variants directory. BUG=b:140068267 TEST=./build_packages --board=drallion Confirm that drallion still builds successfully. BRANCH=none Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Signed-off-by: Mike Wiitala <mwiitala@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-15AGESA: Disable boards from buildKyösti Mälkki
As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y is a mandatory feature, which most AGESA and binaryPI boards lack. Disable such platforms from the build for the time being. The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y. If a platform does not reach ROMCC_BOOTBLOCK=n within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-15asus/f2a85-m: switch away from ROMCC_BOOTBLOCKIdwer Vollering
Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-15mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state functionElyes HAOUAS
Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-15mb/roda/rk886ex: Don't rewrite pnp_{enter,exit}_conf_state functionElyes HAOUAS
Change-Id: Ie9918e5114bb880e37680a85eab2bd224b0b082c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-15mainboard/google/puff: Toggle on DqPinsInterleavedEdward O'Callaghan
BRANCH=none BUG=b:146172098 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2019-12-14asrock/e350m1: Switch away from ROMCC_BOOTBLOCKDenis 'GNUtoo' Carikli
Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-13gizmosphere/gizmo: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
No special treatment required for bootblock. Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37452 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13pcengines/apu1: Switch away from ROMCC_BOOTBLOCKMichał Żygowski
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() callKyösti Mälkki
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-12mb/google/nocturne: adjust VBT boot resolutionMatt DeVillier
On nocturne, the VBT specifies that the native panel resolution (3000x2000) is to be used by FSP/GOP init, which makes payload and grub menus extremely difficult to read. Change the default POST resolution specified by the VBT to 1500x1000 instead (200% scaling) which is much more legible. Test: build/boot nocturne with GOP init and Tianocore payload, observe menu text is actually readable. Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12AGESA, binaryPI: Remove generic device for SPD eepromsKyösti Mälkki
These entries have no functional purpose, followup work will disallow chip entries that do not link in the respective driver. Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12mb/google/hatch/variant/akemi: Increase Goodix touch screen reset delay timePeichao Wang
Confirmed with Goodix team, so increase reset delay time from 120ms to 150ms. BUG=b:144267684 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I4ff95ac89314fc031620ca28e4f6e6e26cdef3f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37544 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12mb/google/hatch: Add new SKU ID 3 and 4Peichao Wang
1. SKU ID 1 and 3 for eMMC 2. SKU ID 2 and 4 for SSD BUG=b:144815890 BRANCH=firmware-hatch-12672.B TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-bootimage Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I25f0c4142be024ba55f671491601d1f6ec26d68a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37498 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12mb/**/hda_verb.c: Clean up formattingAngel Pons
Change-Id: Ibe2d92990d0074266aa05ada749e9dad55e609a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-12hp/pavilion_m6_1035dx: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
No special treatment required for bootblock. Change-Id: I0036614579045b62829577bb2ae94266b2d62310 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37500 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12lenovo/g505s: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
No special treatment required for bootblock. Change-Id: Icb673bba1ba210a077e9569de70b6c4f3cbd1e6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37499 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12asrock/imb-a180: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11pcengines/apu2: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch. The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage. TEST=boot apu2 and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/lenovo/t410: Select ricoh driverPatrick Rudolph
Fix for CB:35086. Build the Ricoh SDcard driver that is defined in devicetree. Change-Id: Ib0ac3da088d798c35e2c5ea045ea721c89d9e12f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37625 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/{facebook/portwell}: Remove empty onboard.hFrans Hendriks
Defines in onboard.h are moved to other files. Remove this empty and unused file. BUG=N/A TEST=build Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/facebook/fbg1701: Move verified items to board_verified_boot.hFrans Hendriks
Items in onboard.h are related to verified or measured boot. Move the items to board_verified_boot.h and remove onboard.h. BUG=N/A TEST=build Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37614 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11fmap: Make FMAP_CACHE mandatory if it is configured inJulius Werner
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-06 05:01:59 +0000