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2019-01-03mb: Remove duplicated ENABLE_VMXElyes HAOUAS
ENABLE_VMX is CPU specific and it is already enabled here: src/cpu/intel/common/Kconfig Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-03mb/google/hatch: Make WP_RO range align with winbond specificationSubrata Banik
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build for hatch. Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30552 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03mb/google/dragonegg: Make WP_RO range align with winbond specificationSubrata Banik
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build and boot dragonegg. Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30551 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-02mb/google/octopus/variants: Add 20ms reset delay for WACOM deviceMarco Chen
Add reset delay in power resource to prevent from failing to bind after unbinding. And boards including yorp series - bobba / phaser and bip series - ampton are affected. BUG=b:121286833 BUG=b:117474421 BUG=b:121019320 BRANCH=None TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/30422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-01mb/google/hatch: Enable CNVi Wifi for hatchMaulik V Vaghela
This patch enables CNVi wifi for hatch 1. Enable CNVi device in device tree 2. Configure GPIO pad config for CNVi BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30436 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-01mb/google/hatch: Add NC gpios for display and correct the orderMaulik V Vaghela
Correcting order of display related GPIOs and also adding not connected pin definitions for display GPIOs BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-31mb/google/hatch: Enable NVME support for HatchV Sowmya
This patch enables the x4 NVME device for hatch, * Enable the Root port 9. * Assign the usage type for clock source. * Configure the GPIO for CLK SRC 1. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30431 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Add the USB port configurationV Sowmya
This patch adds the configurations for, * USB 2.0 ports. * USB 3.0 ports. * Enables USB xHCI controller. * GPIO config for USB2_OC2 and USB2_OC3. * Add the ACPI objects to configure USB ports. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30457 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Enable SATA for HatchV Sowmya
This patch enables the SATA for hatch, * Enable the SATA port 1. * Configure the GPIO for SATA. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30435 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29mainboard: Add Supermicro X10SLM+-FTristan Corrick
This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-29mb/google/glados/variants/caroline/devicetree.cb: Remove unneeded white spacesElyes HAOUAS
Change-Id: I7fdf8934187d2786fdac23ed4460147867c25044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-29mb/google/octopus: Override emmc DLL values for FleexBora Guvendik
New emmc DLL values for Fleex. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Id0022e9d0f0a7802113bbf193decff3c8aaa04f8 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30226 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29mb/google/sarien: Adjust GPD3 pin terminationLijian Zhao
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Reviewed-on: https://review.coreboot.org/c/30374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-29mb/google/hatch: Enable Host Bridge/CSME/PMC/P2SB/SMBusRizwan Qureshi
* Enable host bridge. * Enable CSME. * Enable Power Management Controller. * Enable Primary to Side Band Bridge Controller. * Enable SmBus Controller. BUG=b:120914069 BRANCH=None TEST=code compiles with the changes Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-28mb/pcengines/apu2/romstage.c: disable SVI2 wait completionKrystian Hebel
On some platforms SVI command completion is not reported by voltage regulator. Because of that CPU got stuck in invalid P-State, which resulted in lower frequency and inability to reboot platform without performing cold reset. Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-28mb/google/poppy/variant/nami: add the vbt setting for bard skuRen Kuo
Modify the vbios's eDP signal setting from level0(0dB) to level1 (3.5dB) for bard Add VBT blobs and include it in cbfs BUG=b:119448457 TEST=Test & measure eDP signal Change-Id: I0b854a6adad43844282aed61d26e798727b5cb62 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30375 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28intel/gma/Makefile.inc: Add a helper function to add VBT binariesArthur Heymans
This adds a convenient helper function to add vbt binaries to cbfs. Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30430 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28sb/intel/lynxpoint: Handle H81 only having 6 PCIe root portsTristan Corrick
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/octopus: Override emmc DLL values for PhaserBora Guvendik
New emmc DLL values for Phaser. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30144 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mainboard/google/poppy/variants/rammus: Fixed touchscreen function failedKane Chenffd
According to issue tracker b:119238959 #4 & #6. Hardware modify design to make GPP_E3 to be a switch of touchscreen I2C CLK and SDA. Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during power on initialization to avoid data transfer during this time. After touchscreen IC initial complete, control GPP_E3 to high to make touchscreen I2C CLK and SDA work normally. Depending on touchscreen IC specification, device take 105ms for power on initialization. Change delay time from 120ms to 105ms. BUG=b:119238959 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, run S5 stress test and verify the result Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86452c1445243c499aeaf931dba286db169c5628 Reviewed-on: https://review.coreboot.org/c/30180 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki
Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/hatch: Enable SPI controller for HatchRizwan Qureshi
Enable SPI controller(D31:F5). BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-28mb/google/hatch: Enable console UARTMaulik V Vaghela
This patch incorporates following changes to enable console on UART0 1. update default console number to 0 2. Enable PCI port for UART0 GPIO configuration will be done by coreboot based on correct console number. Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-28mb/google/hatch: Enable LPC/eSPI controllerAamir Bohra
Enable LPC/eSPI controller(D31:F0). EC would be using eSPI interface, since the strap GPP_C5 is pulled up. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-27mb/google/hatch: Add SMI handlersAamir Bohra
Add SMI handlers for below SMI events: 1. eSPI SMI event. 2. ACPI enable/disable SMI event -> Add support for EC to configure SMI mask on ACPI disable. -> Add support for EC to configure SCI mask on ACPI enable. 3. Sleep(S3/S5) SMI event -> Add support for EC to configure wake mask for S3/S5 event Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add HPD GPIO support for displaysMaulik V Vaghela
Adding hot plug detect GPIO support for external Type-C display in event for cable connect/disconnect. Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30365 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-25mb/google/hatch: Modify hatch SPI flash layoutV Sowmya
This patch modifies the hatch flash layout to support IFWI 1.6 with the following regions, Flash Region 0: Descriptor [0x0 - 0xFFF] Flash Region 1: IFWI (consist of ME and PMC FW) [0x1000 - 0x3FFFFF] Flash Region 2: BIOS [0x1400000 - 0x1FFFFFF] Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30413 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-25mb/google/hatch: Enable EC LPC interface and configure IO decode rangeAamir Bohra
Enable EC LPC interface and configure below LPC IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add SoC and EC asl files in DSDTAamir Bohra
This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add EC trigger events and acpi configsAamir Bohra
This implemetation adds EC SCI, SMI, S5/S3 wake trigger events. Also adds the EC specific ACPI configs to enable support for ALS, EC PD device and PS2 keyboard device. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30281 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24mb/asus/p5qpl-am: Add mainboardArthur Heymans
This mainboard has the BSEL straps hooked up to the SuperIO similar to the ASUS P5GC-MX and might therefore require a restart. Tested: - FSB 800, 1067 and 1333MHz CPUs - USB - Ethernet - Serial - 2 DIMM slots - SATA - Libgfxinit (VGA) TESTED with SeaBIOS (sercon disabled) and Linux 4.19. Change-Id: Id845289081751ff8900e366592745f16d96f07c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-24drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT`Tristan Corrick
Any board that uses the AST driver will have support for native graphics init. So, select the option in the driver instead of every board. Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings"Sumeet Pawnikar
This reverts commit 969ed357f823659a6861a2ca38f3ad9d7b58f949 Reason for revert: According to partner issue b:112448519 comment#80, it impacts skin temperature specifications. Change-Id: I7603c3816f34adebc1f67eff6fad214557544022 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-23mb/google/hatch: Enable IGD (Integrated GFX Device)Maulik V Vaghela
This patch ensures following 2 features 1. Enable IGD controller in devicetree.cb 2. Pass required FSP UPD to perform internal graphics initialization Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-23mb/google/hatch: Add memory init setup for hatchAamir Bohra
This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22mb/google/hatch: Enable Elan TrackpadShelley Chen
BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc" emerge-hatch coreboot Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-22mb/google/hatch: Fixes to initial hatch mainboard checkinShelley Chen
Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22cbmem: Always use EARLY_CBMEM_INITKyösti Mälkki
Wipe out all remains of EARLY/LATE_CBMEM_INIT. Change-Id: Ice75ec0434bef60fa9493037f48833e38044d6e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-22emulation/qemu-{i440fx,q35}: Don't migrate globalsArthur Heymans
Migration of globals is not needed as there is no real CAR that gets torn down. Change-Id: Id24642b49fab811e59291747eda8632cd49d83d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-22Revert "mb/google/octopus: Add custom SAR values for Bobba"Justin TerAvest
This reverts commit a914152fa6072c443ccd18de22412b47a228e754. Reason for revert: According to the partner on this project, custom values like this are no longer necessary. Change-Id: I393eb4997f58abe0f77161999474994f06741519 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-21mb/google/sarien: Disable pcie interface for wwanLijian Zhao
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12. BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2018-12-21mb/intel/coffeelake_rvp: Update default configurationWonkyu Kim
Report correct board information for Whiskeylake RVP to OS. Use short board name like other RVP as it's used for firmware version check in auto test. Change-Id: I3f7c95f136e39b978a335cc7855cac819043db7c Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/30318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-21mb/google/poppy/variants/atlas: Remove duplicate entry of dptf_enableSumeet Pawnikar
Remove duplicate entry of dptf_enable. BRANCH=None BUG=None TEST=None Change-Id: I3ddd6a702180624d31c5c58c71acdce8f627c925 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPDFrank Wu
Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A256M16LY-075F SPDIvy Jian
Add SPD file for sdp micron_dimm_MT40A256M16LY-075F (ram id: 11) BUG=b:120884302 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Icf731bfefd550e9b94b6404bc870d4d76451deb1 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/pcengines/alixxx: Drop boardsArthur Heymans
These boards are still using LATE_CBMEM which was agreed upon to be removed after release 4.7. It is now more than 1 year later and they still linger around. The work and review to bring those boards up to date can happen on the 4.9 branch and then squashed and merged back into mainline when done. Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-21mb/google/hatch: Enable H1 TPM support over SPI interfaceAamir Bohra
Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/hatch: Clean up gpio definitions in hatch variantAamir Bohra
This implementation cleans up gpio configuration functions and limit definition to baseboard only for now, until variant specfic overides are needed. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30291 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD"Jenny TC
This reverts commit 999b916015ea0558e3821bdb51501b43a60b5ed6. The DMIC doesn't have an ACPI id. The patch which enables ACPI device with id DMIC may create conflict in the feature. Also the ACPI id "DMIC" doesn't comply with ACPI naming conventions. The issue for which the patch was introduced, is already addressed in kernel DMIC driver and the patches are upstreamed in to the Linux kernel. Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/c/30151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-12-20mb/intel/kblrvp: Change HDA verb table selection logicPraveen hodagatta pranesh
All the kaby lake variants uses HDA verb table except RVP8, hence unselect SOC_INTEL_COMMON_BLOCK_HDA_VERB for RVP8 and enable for other variants by default. BUG=None TEST= Tested on KBL RVP11 and verified the audio functionality. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I64d18ab62cfc08b5560dbcf1b77e975eb68c8d30 Reviewed-on: https://review.coreboot.org/c/30267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-20 14:27:12 +0000