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2020-01-27mb/google/dedede: Enable ECKarthikeyan Ramasubramanian
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:144768001 TEST=Build Test. Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-27mb/google/dedede: Enable building for Chrome OSKarthikeyan Ramasubramanian
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:144768001 TEST=Build Test Change-Id: Ibb94849a903e4d4364d817de8988a430cd717e4c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-27mb/google/dedede: Add smihandler stubKarthikeyan Ramasubramanian
Add stub implementation of smihandler. BUG=b:144768001 TEST=Build test. Change-Id: I7ab25888812bfb4578915e342b14355ccd15f5cc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-27mb/google/dedede: Enable ACPI and add ACPI tableKarthikeyan Ramasubramanian
Enable ACPI configuration and add DSDT ACPI table. BUG=b:144768001 TEST=Build Test Change-Id: I0aa889cd52bff3e1e9ff7b7b93ec1000045bcfd2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-27mb/google/dedede: Add GPIO stubsKarthikeyan Ramasubramanian
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:144768001 TEST=Build Test Change-Id: I1397b6a433e5046650f64f7eb9a84c51eb0c7441 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38278 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-26mb/lenovo/x201: Remove dGPU PMH7 bitsArthur Heymans
The bits cleared by this have to do with dGPU power, which this board lacks. TESTED: x201 still boots. Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36911 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25mb/intel/tglrvp: Enable rp11 for optaneWonkyu Kim
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins. This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-25soc/intel/tigerlake: Fix GPIO communitiesShaunak Saha
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO comuinities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel Tiger Lake Processor PCH Datasheet with Document number:575857 and Chapter number:27. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl verify INTC34C5:0<1-3> listing all the pins for each community. e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list all the community 0 pins. Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-24mb/google/drallion: Remove fixed IccMax valuesJohn Su
Remove fixed IccMax values for U22 CPU. IccMax will be selected by CPU SKU. BUG=b:148110226 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked IccMax[1]. Change-Id: Ifcd31ad5b608ce599d4294a6522fdda022f8a177 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-01-24mb/portwell/m107: Remove mainboard sleepstates.aslWim Vervoorn
BUG=N/A TEST=build Change-Id: Ifb45bc1f7f4d3744124d6797fb4c791fd5f227ca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-24mb/intel/tglrvp: Enable SATAWonkyu Kim
Enable both SATA ports for TGLRVP. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
1. Add a TEMP_SENSOR3 2. Update DFPS (fan performance state) table with values received from thermal team 3. Update PL1 override to 15W 4. Update PL2 override to 51W BRANCH=hatch BUG=b:147792204 TEST=build and verify by thermal team Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22mb/google/hatch: Kohaku: Add MKBP to suspend wake eventsTim Wawrzynczak
This CL allows MKBP events from the EC to wake the system from suspend states. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=Verify that MKBP events generated from EC will wake the system from S0ix. Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-22mb/facebook/fbg1701: Remove ACPI S4 supportWim Vervoorn
Align the fbg1701 sleepstates implementation with monolith. BUG=N/A TEST=build Change-Id: I3a715781bf51da41d6954463ad38ed94b0dfd217 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22mb/facebook/monolith: Disable S3 and S4Wim Vervoorn
The monolith board doesn't support the S3 and S4 states because of the watchdog and failover mechanisms. Remove S3 and S4 from the available sleepstates. BUG=N/A TEST=build Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-21mb/google/puff: Add ac/dc loadline configuationsJamie Chen
According to VRTT report, add ac/dc loadline configuations in puff device tree. BUG=b:147206535 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to puff and checked the log. All ac/dc loadline configs were set correctly. Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-21mb/google/hatch/var/jinlon: Remove DPTF fan controlWisley Chen
Jinlon will use EC to control fan, so remove DPTF fan control. BUG=b:141259174 TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I8ada4fe72eee260fecf45d00510da8b91e3f10a4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/lenovo/t410/Kconfig: Don't select ONBOARD_VGA_IS_PRIMARY explicitlyPeter Lemenkov
ONBOARD_VGA_IS_PRIMARY is selected if board selects DRIVERS_LENOVO_HYBRID_GRAPHICS. See commit 35abe73e with Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff ("mb/lenovo/t430: Fix Dual Graphics"). Change-Id: I39687e5cd34979fd4318978f5aa46ac6cdf721e8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)Ivan Vatlin
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/pcengines/apu2/mainboard.c: Add SMBIOS type 16 and 17 entriesMichał Żygowski
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I45bb2fc36cf0c01670e9fc8559d3a6183ea271f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-21biostar/a68n_5200: Switch away from ROMCC_BOOTBLOCKMike Banon
Following the example of change CB:37737 (ee8f969). Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c'. Tested-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-21mainboard/hatch: Fix puff USB ACPI names and typesEdward O'Callaghan
Fix devicetree to advertise the correct USB names and types in the generated ASL. BUG=b:146437991 BRANCH=none TEST=booted and inspected the reported generated ASL. Change-Id: I133b4db444f9a5f0a36d8e976ae490f24cf307d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-01-20mb/lenovo/x201: Support undock button on X200 ultrabaseMaciej Matuszczyk
Only the ACPI code needs to be extended, as smihandler.c already supported it. The _Q50 Method is just _Q18 with changed name. On Linux, pressing the undock button does nothing, so the only safe way to undock is to press Fn+F9. With this patch, when the undock button is pressed, the green LED lights up, and undocking is safe. Change-Id: Iaaecad031bb1f39dd1a778d0c8eaea6bce9e0f57 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38446 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20mb/pcengines/*: enable simple IO-based GPIO controlPiotr Kleinschmidt
Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address unused by any peripheral for GPIO use. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-20mb/facebook/monolith: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=tested using fwts on a facebook monolith. Found-by: fwts 19.12.00 Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20{mb/facebook/fbg1701,mb/portwell/m107}: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=build Found-by: fwts 19.12.00 Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20mb/hp/snb_ivb_laptops: Switch to overridetree setupAngel Pons
NOTE: The ME interface was disabled on folio_9470m and revolve_810_g1. It is assumed that they were ported while the ME was in an abnormal state (usually due to me_cleaner usage), and that it should be enabled. In any case, the MEI device is hidden if the ME fails to boot already. Change-Id: Ibf32a034653946f49f72a2c19c41a4033964ef83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/revolve_810_g1: Transform into variantAngel Pons
Update Makefile.inc so as to add the SPD data when needed. Tested building other variants, no spd.bin gets added because they don't select GENERIC_SPD_BIN. Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I0cda3f839baa227ce6a4b8f0510934125e5afb59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/folio_9470m: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I65696c5739469b33253c22c1d5a65cc31ef3a421 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8770w: Transform into variantAngel Pons
Since this board does not have integrated graphics, do not install the INT15 handler if it is not selected in Kconfig. NOTE: Since cmos options are not very flexible, this board ends up with a spurious gfx_uma_size option. Other than that, everything is the same. Tested with BUILD_TIMELESS=1, binary does not change when ignoring the cmos options. Change-Id: I2ebcfd5160773bf98a3d23e797a89e290063d112 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8470p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I6dbecb0b4d38ed4af8966f5391fce1f2c9c5d182 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8460p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I17b6ac9ac2433b760e125a1ce708d3b422b632b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/2670p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: Idc4d0a3d7384ad4e5a3eb3d7ecefaa2f35093ac0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/2570p: Transform into variant-enabled structureAngel Pons
Get ready to squash all the HP Sandy Bridge and Ivy Bridge laptops together, so as to factor out lots of repeated code. Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I0b68e524b57e3705e91e3cd98be5571b3554bd67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-19mb/google/kahlee/treeya: Update STAPM parameters for TreeyaPeichao Wang
Change stapm percentage to 80 and time to 2000 seconds make DUT meets Lenovo spec and pass CTS respectively. BUG=b:147333429 TEST=build firmware and install it to DUT and run CTS relevant test, check temperature whether meets spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6a2f059fbd5c89f897cfb46d1f7a82b0923edb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38443 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18google/eve: tweak VBT settingsMatt DeVillier
- Disable Windows driver DPST function - Set POST resolution to 1800x1200 - Set POST brightness to 225 (0-255 scale) Test: Boot Windows on EVE, verify display backlight control functional and no lock ups from switching in/out of tablet mode. Change-Id: Ida64a44df2449f1ff0dc5c8d0ec7b40a183566a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mainboard/google/puff: update SATA strengthTim Chen
Base on SATA SI report to fine tune the strength for port 1. BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine. Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18mb/facebook/monolith: Enable the xDCI controllerWim Vervoorn
Enable the VBOOT_ALWAYS_ALLOW_UDC option to actually enable the xDCI controller. BUG=N/A TEST=build Change-Id: Ib51f2c82e69db83cebceb71ba5f1305764e0feca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/intel/tglrvp: Update tglrvp_up3 devicetreeRavi Sarawadi
Update Tigerlake RVP UP3 devicetree to reflect devices used by tglrvp_up3. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/intel/jasperlake_rvp: Remove sd card detect gpioMaulik V Vaghela
Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is failing due to this. We will update correct gpio for sd card detect once we have Jasper Lake soc gpio patch. partner bug for tracking: https://ticket.coreboot.org/issues/251 BUG=None BRANCH=NONE TEST='jslrvp' mainboard builds successfully Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-18mb/opencellular/elgon: Fix typoElyes HAOUAS
Change-Id: I6724637c7333ae6be7ada3e8ebe878b2a1061dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-18mb/amd/bettong: Fix typoElyes HAOUAS
Use 'irremovable' over 'unremovable' Change-Id: Id305dbe56a93740abc49d85d11402d1b63989dad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37527 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mainboard/google/puff: update USB configurationJamie Chen
Base on USB SI report to fine tune the strength and correct some OC pin settings. BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine. Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18mb/google/link: drop dummy mainboard_post functionPatrick Georgi
It was never filled it, it probably never will be filled in, so stop the pretense. Change-Id: I7632b763b8518304d36a818ce262cc127f95b9f0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/facebook/monolith: Describe device 4.0 in devicetreeWim Vervoorn
BUG=N/A TEST=build Change-Id: Id7267aa6d4266bb7807fb3c25b5e2704c8d81df7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38430 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Add support to read cpu temperatureWim Vervoorn
Read the CPU temperature from the EC. For this board the EC support is limited to reading the CPU temperature sensor at this moment. Events are not supported. BUG=N/A TEST=tested on facebook monolith using acpidbg The TSR0._TMP method is returning the correct values. Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Update power supply settingsWim Vervoorn
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies according to the information in the schematic. The IccMax for these supplies is lower than the standard supported by the SoC. BUG=N/A TEST=build Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mainboard/puff: Fix ACPI tables to advertise correct featuresEdward O'Callaghan
Provide Puff with it's own copy of ec.h copied from the baseboard/includes however with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. V.2: drop EC_ENABLE_ALS_DEVICE as well. V.3: set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. V.4: drop EC_HOST_EVENT_MODE_CHANGE && provide wake pin for EC for _PRW WoL method V.5: drop EC_HOST_EVENT_KEY_PRESSED BUG=b:147850335 BRANCH=none TEST=builds Change-Id: If13bd124c7229ced996efb841980604d13be09af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-17mb/tglrvp: update gpio pin mux for NVMeWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 02:43:39 +0000