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2012-11-13SandyBridge/IvyBridge: Add IFD and ME firmware automaticallyStefan Reinauer
Right now coreboot's build process produces images that are not booting on actual hardware because they are smaller than the actual flash device and also don't have an IFD nor an ME firmware in them. In order to produce bootable images, you needed a wrapper script / extra step until now. With this change, the resulting coreboot.rom is actually bootable. Change-Id: I82714069fb004d4badc41698747a704bd9fed4da Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1771 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ACPI: Zero pstate/cstate control values in FADTDuncan Laurie
If these values are non-zero then the kernel will issue an SMI for each core (cstate) and package (pstate). Since we don't do anything with these SMI callbacks we can avoid taking the extra SMIs at boot time by zeroing these fields. Change-Id: I3bc5fe0a9f45141d46884cb77ecdfaeaa45d2439 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image. Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-08mainboard/roda/rk886ex: Disable CHECK_SLFRCS_ON_RESUMENico Huber
This makes resume from S3 work again. The check is new and fails on other boards, too. Change-Id: I0ada569e4ba649b9ac82768b0888e16104c621e8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02remove enable_cache() of 3 mainboardsSiyuan Wang
Because enable cache is added at the end of disable_cache_as_ram, ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc ) enable_cache() should be removed. The 3 mainboards are: amd parmer, amd thatcher and tyan s8226 Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1669 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-02Persimmon: disable the unconnected Full-Speed USB portDave Frodin
Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-30AMD SB800: PCIE slots on PersimmonZheng Bao
Enable the PCIE bridge which is connected to the PCIE slot. Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1098 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-10-28IEI PM-LX2-800-R10: Added preliminary mainboard supportRicardo Martins
Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050662496936266123&id=09034367569861123956 Support for the IT8888 PCI to ISA bridge will be added in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1152 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27Take care of NULL chip_ops->nameKyösti Mälkki
Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-26iwave/iWRainbowG6: use 16bit access for a register which is not 32bit alignedSebastian Andrzej Siewior
The PCI registers should be accessed aligned and 0x62 is not 32bit aligned therefore this patch changes it to a 16bit access. Change-Id: I00725a4569f471eedb061834f626911b42e734fb Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1631 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-10-26iwave/iWRainbowG6: remove USE_DCACHE_RAMSebastian Andrzej Siewior
This is not available as a config option anymore. Change-Id: Icac173d62928423a08671321ec21d4af82c5cded Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1630 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-10-24Trinity: Initialize the pointer prior to using itZheng Bao
Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1606 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-10bachmann/ot200: Fix wrong IRQ number for PIRQDChristian Gmeiner
The used FPGA on the device triggers PIRQD for the membrane keyboard. The used linux driver for the keyboard uses the fixed IRQ number of 7. In order not to touch the linux driver and be compatible with proprietary BIOS change the irq_table in coreboot. Change-Id: If5bc929eb48bb1eafd401941ebb7d34cf5862c35 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1571 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-10iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller.Dave Frodin
Change-Id: I35fa94bafcf7c835081b57acf031a2fb334d353d Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1570 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-05Mainboard: Fix IO-HUB link number in Dinar mainboardKostr
According to file "northbridge.c" in family 15h code IO-HUB should be placed on link_lsit[0] in devicetree.cb. This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's. Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0 Signed-off-by: Kostr <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/1540 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-05Use mainboard_interrupt_handlers everywherePatrick Georgi
The previous commit provides a mainboard_interrupt_handlers implementation YABEL with identical semantics to the x86emu one, so let's use it in both cases. This eliminates the need for the int15_install() indirection, so let's drop that, too. Generated using the following coccinelle patch and manual cleanups (empty #if/#endif): @@ type T; identifier FUNCARR; expression INT, HANDLER; @@ -typedef T yabel_handleIntFunc; -extern yabel_handleIntFunc FUNCARR[256]; -FUNCARR[INT] = HANDLER; +mainboard_interrupt_handlers(INT, &HANDLER); @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); ... mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -int15_install(); +mainboard_interrupt_handlers(0x15, &int15_handler); Change-Id: I70fd780d7ebf1564a2ff7d7148411673f6de113c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-04add tyan s8226: add a new mainboardSiyuan Wang
our code supports tyan s8226 now, which has two cpus on the board the cpu socket is C32. The details of tyan s8226 is: http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=679&SKU=600000190 the test result of this mainboard is: 1) boot Ubunbu 11.10, kernel 3.0.9. there is no err and warnings in dmesg. 2) boot windows7 x64 successfully. 3) use fwts to test the bios, there are 268 pass and 14 failed 4) pcie and usb slots are ok. 5) all network interfaces are ok. Change-Id: I7d8534f20b4f3c16322a5c5ba2e3fba4b4f3e608 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1495 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to ↵Siyuan Wang
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1497 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-17Set SMBIOS mainboard version based on i2c eepromChristian Gmeiner
In the field there are different hardware revisions and some of them have problems with UDMA as a resistor is missing. We can detect this situation in coreboot and e.g. the linux kernel can take this knowledge and disable UDMA. Change-Id: Ib75cad7acedbc1dc65378bb9bfc3f353cbe21427 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-17Add i2c eeprom to device treeChristian Gmeiner
This eeprom is used to store some device relevant informations like hardware revision. Change-Id: I32bda9d5412bc5a96da0edb5ef0b6d1ba4caa2d8 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1511 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-13Mahogany_Fam10: Fixes an apparent ACPI VGA resource collision.Dave Frodin
Without this change 64 bit versions of Windows will BSOD. Change-Id: If39627a179c24184b6c956b3a50f692f8a034d2f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1476 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-12Fix VT8237S USB IRQ routingRudolf Marek
The M2V-MX SE DSDT has been a copy from Asus A8V-E SE, which has VT8237R. But the stuble change in USB interrupt routing went undetected, although I had some USB troubles on the FOSDEM with low speed devices. Change-Id: Ie724df440e0963f6955b3de57e4687f3ddc7f6ef Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/1505 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-06IEI/KINO: Fixes an apparent ACPI VGA resource collision.Dave Frodin
Without this change 64 bit versions of Windows will BSOD. Change-Id: Ica4b79d798a269399341868b1c793ce745aa93fc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1480 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-25Fix mptable build troublesKyösti Mälkki
A missing mptable.c file got passed jenkins, got merged and broke the build. Hopefully finally fix this. Deletes unused files: src/mainboard/asus/dsbf/mptable.c src/mainboard/supermicro/x7db8/mptable.c Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1486 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22LUMPY: Add information to generate MPTABLE from devicetree.cbSven Schnelle
Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1462 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-07Siemens SiteMP: drop add_mainboard_resources()Kyösti Mälkki
Use of lb_add_memory_region() is reduntant with the MMCONF resource being set as reserved. Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1394 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07bd82x6x: Add beep commandsDylan Reid
Move beep commands to board-specific area as they need to be different for different codecs. Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: http://review.coreboot.org/1410 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-05Technexion TIM5690: drop add_mainboard_resources()Kyösti Mälkki
Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1396 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-04AMD Thatcher: Add BIOS callback hook for getting VBIOS Imagezbao
Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1407 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04AMD Parmer: Remove warning.zbao
Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1399 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-03VIA Epia-N: drop add_mainboard_resources()Kyösti Mälkki
The board had HAVE_MAINBOARD_RESOURCES=0 so this was never called. Drop unnecessary includes too. Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1392 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-03Fix mainboard level enable_dev()Kyösti Mälkki
Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard out of the static device tree. This left dev_root->chip_ops unset, and mainboard_ops.enable_dev() was no longer called. Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1374 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-02AMD Thatcher Board based on trinityzbao
Thatcher features: Family 15 trinity FP2. Hudson. close to Parmer. This board and parmer both need to revert the change http://review.coreboot.org/#/c/1359/, and add thatcher's own chip.h,otherwise the mainboard_enable can not be called. Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1382 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-02AMD and GFXUMA: move setup_uma_memory() to northbridgeKyösti Mälkki
UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1379 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01AMD and GFXUMA : drop redundant use of lb_add_memory_range()Kyösti Mälkki
See commit 505414a6cfb2aeef455b5144e4b96fc27f19eb39. Change-Id: Icc04af9726ae54141581aecc84c40e8aac54591d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1378 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1238 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26amd/lx: Move configuration from source to KconfigPatrick Georgi
LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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