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2014-12-06vendorcode/amd/agesa: Make Porting.h common between familiesEdward O'Callaghan
Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7594 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-06mainboard/lenovo/g505s/Kconfig: Has no SuperIOEdward O'Callaghan
Change-Id: I30fdfb70506241838436c3afbf6ddfdbff5cb302 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7668 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-06mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX portsEdward O'Callaghan
Rather than have Linux report: i8042: PNP: No PS/2 controller found. Probing directly. and go off probing PNP config space, build in EC ASL for the PS/2 keyboard and mouse. The ASL explicitly passes these resources to the Linux to avoid said probe. ASL Details: PS/2 keyboard (PNP0303 at 0x60,0x64 irq 1 ) PS/2 mouse (PNP0F13 at 0x60,0x64 irq 12) Change-Id: I0697fab65915907fbe2b3551182b3a1b0d665ddb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7651 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06mainboard/lenovo/g505s: Toggle on IOMMU supportEdward O'Callaghan
Toggle on in devicetree.cb and build into AGESA by buildOpts.c. Add ACPI and MPTABLES interrupt routers for IOMMU also. Change-Id: Ia838f9b70f09ed1180daeb5382edc08c4b74946c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7643 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06mainboard/*/acpi/superio.asl: Use non-local inclusion syntaxEdward O'Callaghan
Use non-local inclusion syntax over relative paths for 'drivers/pc80/ps2_controller.asl'. Change-Id: Ie2bfa893dc268ec5118d2a9addadbc759d85d357 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7664 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-06mainboard/lenovo/g505s/buildOpts.c: Trivial variable renameEdward O'Callaghan
Minor fix to avoid confusion, nothing to see here. Change-Id: I89d56a91d2df049e85cf49c23218620caba84880 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06fsp_baytrail: Allow selection of USB controller by get_optionMartin Roth
It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06intel/minnowmax: Update devicetreeMartin Roth
- Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7663 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05minnowmax board: Update KconfigMartin Roth
- The ROM chip is 8MB, not 4MB. - Default to the 2GB SKU instead of 1GB - that's what's out right now. - Set CBFS size to 3MB - that's what the firmware descriptor is set to. Change-Id: Ic77f5c1e898dca39de573623707ff5f5e5ca9682 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2014-12-05lenovo/g505s: Kconfig: Remove unused PIRQ legacy bitsEdward O'Callaghan
Since this board does not provide a PIRQ table. Change-Id: I1068dd99c4cecdd2113484fe24ae2bb86a058cb3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7644 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-04RISCV: get RISCV to build againRonald G. Minnich
This makes lzmadecode 64-bit clean (I hope). It also cleans up a few other nits. Change-Id: I24492e9f357e8d3a6de6abc351267f900eb4a19a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7623 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-04via/epia-n: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ica4d49b9f4f192b1544ba8cbd5f28a4019259be0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6942 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03i82801gx: Enable upper CMOS in bootblock.Vladimir Serbinenko
Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03mainboard/hp/pavilion_m6_1035dx: Remove HUDSON_LEGACY_FREEEdward O'Callaghan
The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: Ia487d21faa0fceb2557dbce14ef8822116fada91 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7628 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-03mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREEEdward O'Callaghan
The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7625 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam14: Move agesawrapper_amdinitmmio()Kyösti Mälkki
Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA: Trace execution with AGESA_EVENTLOG()Kyösti Mälkki
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7604 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Common agesawrapper for S3 resumeKyösti Mälkki
Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Remove duplicate OemCustomizeInitEarly declarationsKyösti Mälkki
Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7158 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam15tn / fam15rl / fam16kb: Common agesawrapperKyösti Mälkki
Split FCH parts to southbridge/hudson. Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7159 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial portKyösti Mälkki
Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7602 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam14: Common agesawrapperKyösti Mälkki
Use copy of amd/persimmon. Change-Id: I7404cb164df9065bcdbaaf5367018870ea675adc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7157 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA fam12: Common agesawrapperKyösti Mälkki
Change-Id: Ic44d827323dc0d3c776e79c22088a2f1f654bcf2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7156 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA fam15: Common agesawrapperKyösti Mälkki
Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a common file for now and split eventlog parser to a separate file. Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7155 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA fam15: Move LPC decode enable for serial portKyösti Mälkki
Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA: Report events with AGESA_EVENTLOG()Kyösti Mälkki
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may fall through critical failures. Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7154 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Use common header for agesawrapperKyösti Mälkki
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7153 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetreeKyösti Mälkki
GPP config from devicetree.cb is not implemented for fam15tn/fam16kb. Also only for asus/f2a85-m the configuration value matched the actual programming. Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7600 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA Hudson/Yangtze: Remove obsolete devicetree parametersKyösti Mälkki
Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7599 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02cubieboard: use new arm bootblock infrastructureAlexander Couzens
commit 8b685398 (ARM: Overhaul the ARM Makefile.) change config flags for cpu and mainboard bootblock initialization. Tested on a20/cubieboard2. Change-Id: I2a1019c2881bc7aada15322841204992d0106453 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7188 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich
Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30gigabyte/ga-b75m-d3h: Add new Intel mainboardDamien Zammit
This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS. Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7341 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-29mainboard/intel/minnowmax: use Baytrail Gold3 FSPYork Yang
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. See commit a0b4a8d. Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7465 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-28mainboard/lenovo/g505s/devicetree.cb: Fix duplicate typoEdward O'Callaghan
Change-Id: Ic2b8ca54b9a16c13439b3081969deec0b7187e01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27mainboard/lenovo/g505s: New port Richland APU A10-5750MEdward O'Callaghan
Richland APU A10-5750M 8GB RAM 4MB Flash Boots to working Linux with SeaBIOS payload. S3 works with Linux 3.16.3-2 Debian Jessie. Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7560 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26sandy/ivy: Remove explicit setting of HAVE_SMI_HANDLER.Vladimir Serbinenko
Southbridge already selects it, no need to repeat. Change-Id: I9a5ad553f48e30103371cc2d896168ae4abfb8ef Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7570 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-26agesa/family12: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I944e35b04612eca8add80c9f546df99a9a930ac8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26agesa/family16kb: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I7d9cbbd1aeadecc1a4c91816df303c6cb4817fe3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26agesa/family15tn: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Icc2e7b66b3ff5f70b219a3e67494ce3df055c9d5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-26agesa/family15: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I3847eb1524a5a816cd4885a31d703b410804c1f0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-25agea/family14: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Icc663c28713f2d872bfeb1749303ce92db953bf5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7031 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-25lenovo/t60: Remove PIRQ table.Vladimir Serbinenko
This was copied from P2B-F without doing any modification. It never worked. Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Change-Id: I2c90688c8ff8c3bd272d24f059e8e1bfb86e2b4a Reviewed-on: http://review.coreboot.org/7555 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-25getac/p470: Change COM3/COM4 IRQ to move it out of PCI IRQ ones.Vladimir Serbinenko
The suggested IRQs 10 and 11 would conflict with PCI IRQ assignment (10 for most interrupts on this board). Suggest IRQ 6 instead. It's actually a noop since the code is commented out. Change-Id: I0fdd8e2091d3dc79cfb1809a9ea5e1e841ca598a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7476 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-25google/butterfly: fix off-by-one issuesPatrick Georgi
GPIOs 32 and 64 used the wrong code path. Change-Id: I1d293cf38844b477cac67bc19ce5e5c92a6e93ca Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7577 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-05 21:30:38 +0000