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2016-10-06google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configurationJeffy Chen
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-06rockchip/rk3399: Move big CPU cluster initialization into ramstageJulius Werner
This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-05siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 msWerner Zeh
Due to different LCD panel requirements the delay between LVDS becomes active and the backlight is switched on needs to be increased to 500 ms. Change-Id: I09029624469aef412141c7b46224d48557ba4af1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16875 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04google/gru: Ensure correct pull resistors for special-function pinsJulius Werner
Several of the special function pins we're using in firmware have a pre-assigned pull-up or pull-down on power-on reset. We don't want those to interfere with any of the signaling we're trying to do on those pins, so this patch disables them. Also do some house-cleaning to group the bootblock code better, and change the setup code for all SPI and I2C buses to first initialize the controller and then mux the pins... I assume this might be a little safer (in case the controller peripheral has some pins in a weird state before it gets fully initialized, we don't want to mux it through too early). BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560 Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382532 Reviewed-on: https://review.coreboot.org/16711 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04gru: Increase SPI speed to 33MHzSimon Glass
Increase the SPI bus speed to speed up boot time. The maximum supported speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed, given the clock parents. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. Total time spent on reading from SPI reduces from 185ms to 141ms. Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381313 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04google/gru: Init the PWM pinmux after setting up the PWMDouglas Anderson
If we setup the PWM _after_ the pinmux then there's a period of time when we're driving the PWM incorrectly. Let's setup the regulator and _then_ configure the pinmux. This fixes no known bugs, but it is more correct and probably makes the signals look better at bootup. BRANCH=None BUG=None TEST=scope Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1 Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381592 Original-Reviewed-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16700 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04mainboard/siemens/sitemp_g1p1: Use tabs for indentsElyes HAOUAS
Change-Id: Ia5ea2198cdc93822723a4fe5440d574d76cb4de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04nb/gm45: allow use of 352M preallocated ram for igdArthur Heymans
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04mainboard/amd/torpedo: Improve code formattingElyes HAOUAS
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/mainboard: Remove unnecessary semicolonElyes HAOUAS
Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16859 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-10-04samsung/lumpy: Swap SPD assignmentsKyösti Mälkki
On-board memory is on channel 1. This fixes native raminit with 4GiB SO-DIMM installed. Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/16845 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-03google/gale: Remove #ifdef of Kconfig bool symbolMartin Roth
Kconfig symbols of type bool are ALWAYS defined, so this code was always being included and run, which isn't what the author wanted. Change to use IS_ENABLED(), and a regular if() instead of an #ifdef. Change-Id: I72623fa27e47980c602135f4b73f371c7f50139b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-03google/gale/Kconfig: Change wording of Kconfig optionMartin Roth
Everybody knows WHAT they're supposed to do with options, so the text "Pick this" or "Select to" are redundant. Change-Id: I327c5be755373e99ca0738593bd78e1084d4d492 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-02mainboard/packardbell/ms2290: Use tabs for indentsElyes HAOUAS
Change-Id: I1559a2541a93a9969ac68708a04f0468790feb69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16844 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02mainboard/via/vt8454c: Improve code formattingElyes HAOUAS
Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16843 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02mainboard/apple/macbookair4_2: Use tabs for indentsElyes HAOUAS
Change-Id: I2714553e2521f8178538755e3cfadec5c1fc6b12 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16842 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-02apple/imac52: add mainboardArthur Heymans
Add Imac5,2 based on macbook2,1 port. Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mb/kontron/ktqm77: Let suspend LED flash slowly in S3/S4Nico Huber
Change-Id: Idb37abea01831631aadba66ecd42bc7df03aa857 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16727 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01biostar/am1ml: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/biostar/am1ml. Change-Id: Iba2fff5617c62152355b54e446517ad36108aa31 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16688 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-01mainboard/google/reef: Update DPTF policy temp. values for CPUSumeet Pawnikar
This patch increases the CPU specific passive temp. trip point and critical temp. trip point value for DPTF policy. BUG=chrome-os-partner:57903 TEST=Built, booted on reef and verified this passive and critical temp. trip points with heavy workload. Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16766 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
2016-10-01mainboard/google/reef: unconditionally set MAINBOARD_FAMILYAaron Durbin
For all mainboard variants use the "Google_Reef" family by default which is populated in SMBIOS tables. A variant can provide their own value if needed, but "Google_Reef" can reside as the family without having to add conditions for each variant when MAINBOARD_FAMILY have to be overridden. BUG=chrome-os-partner:56677 Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16813 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-01mainboard/amd/serengeti_cheetah: Use tabs for indentsElyes HAOUAS
Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16817 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-01mainboard/*/*/*/usb.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/gigabyte/m57sli/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16815 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/jetway/j7f2: Use tabs for indentsElyes HAOUAS
Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/winent/mb6047: Use tabs for indentsElyes HAOUAS
Change-Id: Iaf5ad440cfc2bbe08ea9f6c545e5e314645c8893 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/kontron/ktqm77: Use tabs for indentsElyes HAOUAS
Change-Id: I3040dc9a2534a77087805ee61c4f91d1bdb4d509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16822 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/digitallogic/msm800sev: Use tabs for indentsElyes HAOUAS
Change-Id: I39ad6606869f059b2ef0c45d6741b844b3791655 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16821 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/gigabyte/ga-b75m-d3v: Use tabs for indentsElyes HAOUAS
Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16816 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/gigabyte/ga-b75m-d3h: Use tabs for indentsElyes HAOUAS
Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/samsung/stumpy: Use tabs for indentsElyes HAOUAS
Change-Id: I1ffee53a04df6874f658feb3d6ce7d5c7b922837 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16818 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/kontron/986lcd-m: Use tabs for indentsElyes HAOUAS
Change-Id: Ibeb0da2f75b4aec32f5238e5634bc1f1d8220b84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16820 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30google/reef: Fix default values in KconfigMartin Roth
These default values weren't being set with the default keyword so were ending up with different values. from the default generated config file before this change: CONFIG_DRIVER_TPM_I2C_BUS=0x9 CONFIG_DRIVER_TPM_I2C_ADDR=0x2 CONFIG_DRIVER_TPM_I2C_IRQ=-1 Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16828 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30Kconfig: Prefix hex defaults with 0xMartin Roth
Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16827 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30mainboard/google/stout/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I2402648b8c0b9dcc730ce7f099e1e4ccef3b79fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-30mb/intel/d945gclf: Allow use of native graphic initArthur Heymans
Add PCI device id to native graphic init and add the Native graphic init option in Kconfig. Change-Id: I136122daef70547830bcc87f568406be7162461f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16512 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mainboard/intel/galileo: Make FSP 2.0 the defaultLee Leahy
Switch from FSP 1.1 to FSP 2.0 as the default build. BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16810 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mainboard/intel/quark: Add FSP selection valuesLee Leahy
Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16785 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16784 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/lanner/em8510: Use tabs for indentsElyes HAOUAS
Change-Id: Ib6191c590144438d7d9d6772d792a83e92d5516a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/iwill/dk8_htx: Use tabs for indentsElyes HAOUAS
Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/gigabyte/ga_2761gxdk: Use tabs for indentsElyes HAOUAS
Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16779 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/elmex: Add new board pcm205401Yuichi Ito
pcm205401 is CPU board equipped with T40R of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205401. In comparison to pcm205400, only VGA PCI ID is changed and board identifier strings in SMBIOS / DMI. Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15930 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29mainboard/elmex: Add new board pcm205400Yuichi Ito
pcm205400 is CPU board equipped with T56N of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205400. I disable the port5, 6, and 7 of the PCI-e in elmex/pcm205400/PlatformGnbPcieComplex.h. I disable the audio capabilities at the 236th line of elmex/pcm205400/platform_cfg.h. Coding style is modified to avoid the error and warning that occur when I commit. Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15929 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29src/mainboard: Add vendor ELMEX with a boardYuichi Ito
Add board with amd/persimmon as template. Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15926 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-28google/reef: Mark touchpad and touchscreen as probed devicesDuncan Laurie
Add the 'probed' flag to the touchpad and touchscreen devices so they are probed by the kernel before being loaded, in case they do not exist or are replaced with another vendor. BUG=chrome-os-partner:57686 Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28mainboard/amd/rumba: Use tabs for indentsElyes HAOUAS
Change-Id: I005e607faa2a6c527584ba9cdcad92f4517a15e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16778 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/supermicro/h8dmr/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I008ccc5fa9d96e52ee59a4562d81e4f7c1d1a6ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 22:11:53 +0000