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2020-04-20mb/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOPMike Banon
Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/33919 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/asus/am1i-a/buildOpts.c: guard UMA-related options with CONFIG_GFXUMAMike Banon
Looks like the guard was dropped by mistake. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33916 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/asus/am1i-a/buildOpts.c: return the removed commentsMike Banon
These comments exist in other buildOpts.c files, but not in this one. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-20mb/asus/am1i-a/buildOpts.c: Use fully-qualified paths on includesMike Banon
This makes it easier to know which files are being included. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenienceMike Banon
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/volteer: Update devicetree based on EDSWonkyu Kim
Update device enable/disable based on PCH EDS#576591 vol1 rev1.2 BRANCH=none BUG=b:154037185 TEST= boot up OS in volteer and check and check lspci Unsupported IP should be visable from lspci result Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/dedede: remove samsung-K4U6E3S4AA-MGCL.spd.hexMarco Chen
The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone yet. On the other hand, the spd content is not correct based on JSL spec as well. BUG=b:153426401 TEST=build waddledoo and waddledee successfully. Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVPRonak Kanabar
Configure write protect and card detect SD Card GPIO for JSLRVP as per schematics. BUG=None BRANCH=None TEST=Build, boot JSLRVP and verified SD Card detection. Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/tglrvp: Configure intel common configWonkyu Kim
Configure lockdown and i2c speed setting. BUG:b:151161585 BRANCH=none TEST=build and boot tglrvp and check FSP logs to lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Enable Cirque touchpad for DeltanEric Lai
Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20mb/google/drallion: Increase Melfas touchscreen stop delay to 115msJohn Su
Modify stop_delay as 115ms to waiting for Melfas device I2C interface ready after touch fw auto update and rebind driver. BUG=b:153708773 BRANCH=drallion Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/qemu-i440fx,q35: Fix option tableNico Huber
Reserve bytes 50 and 55 as they are handled as century bytes by QEMU. Change-Id: I9271253bce560d4ec8a51a24c45473acec469187 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/qemu-q35: Select `HAVE_CMOS_DEFAULT`Nico Huber
Change-Id: If4c4dc9467154a18168550538fc8e655636e87a0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/intel/harcuvar: Fix board_id() return typeJacob Garber
The weak definition of board_id() in coreboot_table.c returns a uint32_t, so update this function to match. This fixes a compiler error when using LTO. Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/lenovo/t420(s): Do minor cosmetic changesPeter Lemenkov
Align the whitespace and do some cosmetic changes. This makes it easier to fold these two boards into a variant setup. Change-Id: I53bdd90ae47b52dfdfec27229c6b904487fa2081 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18asus/p2b*: Declare \_SB.PCI0.MBRS in DSDTKeith Hui
sb/intel/i82371eb/isa.c has code that fills this path with CPU info. Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in Slackware 14.2 complains. Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b*: Move serial init into mainboard bootblockKeith Hui
With this bootblock messages are transmitted over serial too. TEST=Serial messages transmitted normally on asus/p2b-ls. Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18asus/p2b-ds: Transform into variantKeith Hui
TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I864f939a84ee9e90013ba9d3fcc8a7e4bf03e4ee Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39904 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b-d: Transform into variantKeith Hui
TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I1161c726c8c752b5b1e152e1617811989631096e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39903 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b-ls: Transform into variantKeith Hui
Boot tested on hardware. Change-Id: I24afd67dada135a8c2597f5ac1c7e91ce43897c9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39901 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/ocp/tiogapass: Pull POST complete pinBryantOu
Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-04-16mb/google/hatch/var/kindred: Override VBT selection for kledDavid Wu
Override VBT to fix CRC error issue with psr2 panel for kled. Cq-Depend: chrome-internal:2877637 BUG=b:145963505 BRANCH=hatch TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-04-16mb/google/puff: Add variant specific DPTF parametersTim Chen
Modify DPTF parameters for OEM EVT build from thermal team. BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-15mb/google/hatch: Add Kaisa variantAndrew McRae
A verbatim copy of variants/puff V.2: rebased on duffy. BUG=b:152951180 BRANCH=none TEST=none Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/google/hatch: Add Duffy variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/kontron/ktqm77: Extend SATA CMOS option with "legacy" modeNico Huber
TEST=Booted Linux 2.6.12 w/o native Intel IDE driver and confirmed working SATA drive. Change-Id: I85f72a172bcbc4c8b4bfb7a2baed7c6739b2d9f8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15Do not select USE_BLOBSNico Huber
The `USE_BLOBS` config only exists for idealistic reasons. If we would allow us to use blobs by default, we wouldn't need that option and could just always do it. It's generally debatable for the project as a whole, but not per board/subject. Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-15mb/intel/jasperlake_rvp: Update JSLRVP USB configurationRonak Kanabar
Remove extra USB port entry because it came in from copy patch from the previous board and configure USB over-current pins as per JSLRVP. Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/google/puff: Fix up WLAN_OFF gpio configurationEdward O'Callaghan
BUG=b:152927525 BRANCH=none TEST=builds Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/lenovo/x60: Add vboot supportArthur Heymans
It's relatively slow to boot. It takes 1.5s to get to the payload. In timestamps there are entries related to TPM, which are somewhat weird given that the TPM is not enabled on this device (buggy). TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you can force the recovery bootpath. Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15mainboard/puff: Tune ALC5682I rise_fall times on i2cEdward O'Callaghan
Tunes the headphone amp i2c with measured signal shape. BUG=b:147192377 BRANCH=none TEST=builds and measured i2c frequency below 400khz Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14trogdor: Add third RAM_CODE pinJulius Werner
We decided to add a third RAM_CODE pin to the Trogdor family for devices after rev1. This patch adds support to read it. Since the newly used pin was previously unconnected (not pulled down) on rev1, this will change the RAM_CODE result for previous versions (and actually make it undetermined until we enable tri-state). But since we're not actually using RAM_CODE for anything yet, and since those are development revisions that will eventually be discontinued, this should be fine. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-14mb/google/nightfury: Update tdp_pl1_override valueSeunghwan Kim
Update tdp_pl1_override value to 15W for CML-U based nightfury platform. BUG=None BRANCH=firmware-hatch-12672.B TEST=Built Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-14mb/google/deltaur: Enable Melfas touch screen for DeltanEric Lai
Reference Drallion to add device tree for Melfas touch screen. BUG=b:152924290 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14mb/google/octopus/variants/lick: Disable xHCI compliance modeJulia Tsai
Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:153782196 TEST=Verified usb operation successfully. Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/dedede: Enable ELAN touchscreen for WaddledooDtrain Hsu
Add ELAN EKTH6918 USI touchscreen support. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-14mb/google/dedede: Enable SIS touchscreen for WaddledooDtrain Hsu
Add SiS9813 USI touchscreen support. BUG=b:152936541 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/intel/{jasperlake_rvp, tglrvp}: Remove unused filesSubrata Banik
This patch removes unused "spd_util.c" files from mainboard directory. Change-Id: Ibd011be578fa256afb61796d5ceeea073e852fe9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-04-14mb/google/hatch: Use tabs for alignmentPaul Menzel
Change-Id: I38d429245810f64a03253b5076391af843f8d0de Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/google/poppy/variants/nami: Use tabs for alignmentPaul Menzel
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39 Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/ocp/tiogapass: Add missing spaces around operatorsPaul Menzel
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-14mainboard: add Supermicro X9SCL/X9SCMJonathan A. Kollasch
Boots to Linux. Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7 To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants) Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14src/mainboard: Use 'const' to set pnp_devfn_t staticallyElyes HAOUAS
Change-Id: I50ac6914fadc02491df2eccb437eada89fd12b82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14mb/lenovo: Add additional FMAPs on 8MiB devicesMarcello Sylvester Bauer
* Add FMAP for measured boot only, with a single RO partition. * Add FMAP for measured boot only, with a single RO partition but where the ME has been shrunken. Tested on X220 using VBOOT+measured boot: * Used patched IFD and ME, boots into OS Change-Id: I04c1add13198444638c669deec1e05159b1a09c9 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-04-14mb/intel/tglrvp : Enable RP LTRWonkyu Kim
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/volteer: Enable RP LTR settingWonkyu Kim
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/volteer: fix incorrect fields in SPDsNick Vaccaro
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16) This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD). BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel. Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-04-14mb/google/volteer: fix CROS_GPIO_WP_AH exportNick Vaccaro
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community zero instead of community 1. BUG=b:152876091 TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to and log into Volteer kernel, execute "wp enable" in H1 console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in H1 console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14mainboard/lenovo: Use the original hardware ids for keyboard/pointingdalao
Currently coreboot is using the compatible ID PNP0303 for all keyboards and PNP0F13 for all pointing devices, which causes some problems. On Windows, the touchpad driver can't be automatically matched and installed through Windows Update. On Linux, there are some strange issues. So it's better to use the original hardware IDs for each model. The hardware IDs for the following models can be found By searching for dmesg logs on vendor BIOS: T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html Keyboard: PNP0303 Pointing: IBM0057 R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg Keyboard: PNP0303 Pointing: IBM0057 X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out Keyboard: PNP0303 Pointing: IBM3780 X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2 Keyboard: LEN0010 Pointing: IBM3780 T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log Keyboard: LEN0010 Pointing: IBM3780 T510: https://bbs.archlinux.org/viewtopic.php?id=120287 Keyboard: PNP0303 Pointing: LEN0015 T410: https://forum.ubuntuusers.de/topic/kein-sound-109/ Keyboard: PNP0303 Pointing: LEN0015 T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T420s: https://bbs.archlinux.org/viewtopic.php?id=191510 Keyboard: PNP0303 Pointing: LEN0015 T520: https://bbs.archlinux.org/viewtopic.php?id=195636 Keyboard: PNP0303 Pointing: LEN0015 W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log Keyboard: PNP0303 Pointing: LEN0015 T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg Keyboard: PNP0303 Pointing: LEN0015 T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU Keyboard: LEN0071 Pointing: LEN0015 W530: https://bugs.freedesktop.org/attachment.cgi?id=115557 Keyboard: LEN0071 Pointing: LEN0015 L520: https://pastebin.com/U6MaBAY3 Keyboard: PNP0303 Pointing: LEN0017 X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1 Keyboard: PNP0303 Pointing: LEN0018 X220: https://bbs.archlinux.org/viewtopic.php?id=237669 Keyboard: PNP0303 Pointing: LEN0020 X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460 Keyboard: PNP0303 Pointing: LEN0020 X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg Keyboard: MSF0001 Pointing: LEN0026 X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851 Keyboard: LEN0071 Pointing: LEN0030 s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt Keyboard: PTL0001 Pointing: LEN0031 T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg Keyboard: LEN0071 Pointing: LEN0034 X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg Keyboard: LEN0071 Pointing: LEN0035 T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541 Keyboard: LEN0071 Pointing: LEN0036 T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976 Keyboard: LEN0071 Pointing: LEN200e Others: https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c Test result: This can make Windows automatically install the Lenovo touchpad driver. It also fixes the T440p touchpad issue. Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932 Signed-off-by: dalao <dalao@tutanota.com> Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-04 12:54:24 +0000