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2019-01-16AGESA fam15tn boards: Clean up devicetreeKyösti Mälkki
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30734 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: mikeb mikeb <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16AGESA fam14 boards: Clean up devicetreeKyösti Mälkki
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30733 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/sarien: Set PL1 and PL2 valuesSumeet Pawnikar
Set PL1 and PL2 values to 25W and 51W respectively for processor power limits control. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-16mb/intel/kblrvp: Fix unsigned val casting of smaller sizePraveen hodagatta pranesh
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I519ed4b5b403622d6bb01ad0bdd04e01dedff7d8 Reviewed-on: https://review.coreboot.org/c/30794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-16mb/intel/kblrvp: Add new Kaby lake RVP11 supportPraveen hodagatta pranesh
The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform. This patch add following chages - Add overridetree.cb for RVP11 - Select skylake PCH-H chipset config for RVP11. - Add GPIO table as per board schematics. - Add audio verb table for RVP11. - Set the UserBd UPD to BOARD_TYPE_DESKTOP. BUG=None TEST= Build and flash, confirm boot into yocto OS on KBL RVP11 platform. verified PCI, USB, ethernet, SATA, display, audio and power functionalities. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Reviewed-on: https://review.coreboot.org/c/29809 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-16siemens/mc_apl4: Change UART_FOR_CONSOLE indexMario Scheithauer
This mainboard uses SOC internal UART 1 instead of UART 2 like all other mc_apl1 mainboards. Change-Id: Ib986962ed068fee019ffcec0391d43d5ab178458 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/30933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16mb/google/sarien: Set Vref Config to 2Lijian Zhao
Accoding to desciption in FSP header, Vref Configuration will be set to 2 if VREF_CA to CH_A and VREF_DQ_B to CH_B. BUG=N/A TEST=Build and boot up on Arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I02e16e141b81d766a6060ca08283f432abd96647 Reviewed-on: https://review.coreboot.org/c/30280 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15mb/google/atlas: Enable camera module NVMChen, JasonX Z
Enable at24 EEPROM by adding ASL of nvm BUG=b:122583978 BRANCH=master TEST=Build and run for basic camera functions Change-Id: Ifc2060c2ceb7d1a8ef490f36f484deb425a37c95 Signed-off-by: Chen, JasonX Z <jasonx.z.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/30795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-15mb/*/*: Use libgfxinit on sandy and ivy bridge boardsArthur Heymans
Change-Id: I41ad1ce06d9afcc99941affa232fa76ffa6631fb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-15mainboard/ocp/wedge100s: Fix uartPatrick Rudolph
* Route IO 0x6e/0x6f to LPC bus * Setup ITE8526 in early_mainboard_romstage_entry * Fix romstage serial console by disabling internal uart default setting * Unselect CONFIG_INTEGRATED_UART, as it doesn't use internal UARTs * Select CONFIG_DRIVERS_UART_8250IO, as it has a SuperIO serial * Configure UPDs related to serial Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-14[RFC]util/checklist: Remove this functionalityArthur Heymans
It was only hooked up for galileo board when using the obsolete FSP1.1. I don't see how it can be useful... Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30691 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14Revert "mb/google/kalista: Disable EC-EFS"Patrick Georgi
This reverts commit 4e3cd744492c7a3d80bca55a35276efeada731e5. Reason for revert: Daisuke says "We'll keep EFS on Kalista/Karma enabled" Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I2f11ffc9dd7eb05a2560261bbf472e8488c274d9 Reviewed-on: https://review.coreboot.org/c/30857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/asus/p5qpl-am: Add p5g41t-m_lx as a variantAngel Pons
This board has more or less the same as the p5qpl-am except for DDR3 memory and different colors on the ports. Tested with Arch Linux with kernel 4.20.0-arch1-1-ARCH. What is tested and works: - 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz Some bugs are still present in the DDR3 raminit code though. - Ethernet - Internal programmer with both coreboot and stock firmware. - PCI and PCIe x1 slots - All USB ports - S3 resume - SATA ports - PEG - Rear audio output Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/27089 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14/src/mb/google/poppy/variants/atlas: Revise SPK resetGaggery Tsai
This patch revises the pad reset config of speaker reset GPIO pin from RSMRST to PLTRST. Audio engineer suggested to reset the amps with warm reset. BUG=b:122441567 BRANCH=None TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the speakers are working well. Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/30866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-14mb/intel/coffeelake_rvp: Update mainboard UART KconfigWonkyu Kim
Update mainboard UART Kconfig for Whiskylake RVP. TEST=Build and test on Whiskylake RVP. By default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port2. Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled. Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/30861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-14nb/intel/pineview: Move the boilerplate mainboard_romstage_entryArthur Heymans
The mainboard_romstage_entry function is mostly boilerplate, so move it to a common location and provide mainboard specific callbacks. Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE maskedJohn Zhao
PLT_RST_L was asserted twice at boot-up and a glitch was observed when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE from HIZCRx1 to be masked. BRANCH=octopus BUG=b:117302959 TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high 3.3v during S0ix. Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30815 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/google/octopus/variants: Disable xHCI compliance modeJohn Zhao
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:115699781 TEST=Verified usb operation successfully. Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30817 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/google/hatch: Use USB2 Port 10 for BT over CnViAamir Bohra
Integrated BT controller in CnVi uses USB port 10 for communication. BUG=b:122552619 TEST=lsusb shows BT device Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30809 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/lenovo/[xtz]60: Introduce and use RCBA64 macroPeter Lemenkov
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14mb/lenovo/*/romstage: Use macros instead of magic numbersPeter Lemenkov
Apparently coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Note that IOTR[0123] is a 64-bit width variable. Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14sb/intel: Use common RCBA MACROsPeter Lemenkov
This commit follows up on commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()Patrick Rudolph
Move early_mainboard_romstage_entry before console_init. Allows to setup a SuperIO, if any, for serial console. Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14AGESA binaryPI: Consolidate ACPI for IMCKyösti Mälkki
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14AGESA binaryPI: Remove unused IMC ACPI methods IMSP and IMWKKyösti Mälkki
Note that IMC must sleep while SPI writes are in progress. Instead of using these ACPI methods, flashrom currently does raw IO to achieve the same. Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18537 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14binaryPI: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-01-14AGESA: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-14AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLEMike Banon
Only a few boards are using IMC for the onboard fan control, so regarding the availability of IMC selection it should be opt-in, not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2 because Gizmo 2 could use IMC for the onboard fan control. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16 Reviewed-on: https://review.coreboot.org/c/30756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13google/butterfly: correct northbridge selectionMatt DeVillier
butterfly is a Sandybridge device, and selecting Ivybridge breaks libgfxinit currently due to CPU mismatch Test: build/boot butterfly w/libgfxinit Change-Id: I1a7f5a3681d21a256834b11b545855c4365f5f78 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30820 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13google/butterfly: add cpu/gpu pwm backlight register valuesMatt DeVillier
Required for functional internal display on butterfly using libgfxinit. Test: boot/build butterfly, verify internal display functional prior to OS driver loading. Change-Id: Ib8060f2d1ad0694f0886d35c83763907f61b47b1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30819 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13mb/google/kukui: add flapjack on top of kukuiYH Lin
Add placeholder for future flapjack additions/modifications. BUG=None BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e Reviewed-on: https://review.coreboot.org/c/30859 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki
This board is the only user of these ancient chipsets, so we'll do all in one go. Also wipe out some extra headers. Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an adjustment is necessary for this mainboard. Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/30836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10mainboard/google/octopus: configure EC_AP_INT_ODLJett Rink
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. Also removing unnecessary IO standby support since we don't use this pin to wake up the SoC. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30788 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10amdfam10 boards: Simplify early resourcemapKyösti Mälkki
Purpose of the table is to load initial address maps on PCI function 0:18.1. Provide a macro of its own so it is clear no other PCI devfn is accessed here. Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10amdfam10 boards: Drop extern on apicid_sp5100Kyösti Mälkki
The value get_bus_conf() initialises this value to is discarded. Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10google/kukui: Correct boardid sources and add sku_idHung-Te Lin
Kukui is going to use ADC#4 as SKU ID, and utilizing EC BoardID as global board_id (i.e., board revision). BUG=b:122060615 TEST=make; manually tested on Kukui P1 board. Change-Id: I7bba368c141a7ba6db11f24b8e8e7158f0fc729e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10google/kukui: Complete board ID ADC valuesHung-Te Lin
The ID from ADC on Kukui supports 16 different values and we should list all voltage values ahead. BUG=b:80501386 TEST=make; manually verified on Kukui P1 Change-Id: Ic3abe07abfe818ca68e180c262fd431d1167b801 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10google/kukui: Correct boardid init valuesHung-Te Lin
From `boardid.h`, the uninitialized ID values should be BOARD_ID_INIT instead of BOARD_ID_UNKNOWN. BUG=b:80501386 TEST=make; manually verified on Kukui P1 Change-Id: Ie5267e575e38b92ec64a7317defbd00ee153fa0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10mb/foxconn/g41s-k: Add g41m variantArthur Heymans
Was tested with the following: - 2 DIMM slots - USB - Ethernet NIC - automatic fan control - Libgfxinit with VGA, DVI (HDMI slot unpopulated) - PS2 Keyboard - SATA - PEG - S3 resume What does not work: - Using the second DIMM slot on a channel G41 can only handle 2 ranks per channel and on this mainboard 1 rank per DIMM slot. Supporting this would require too much raminit rework and is not worth it (at least for me) Change-Id: I67784038ef929f561b82365f00db70a69c024321 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAPDuncan Laurie
1) Add a Platform Data Region called SI_PDR which is allocated in the flash descriptor for this platform 2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile storage. 3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG so it is clear they are associated. 4) Move the RW_DIAG region to the start of the RW region so that once we can re-enable a larger BIOS region this sub-region will be in the uncached area since it is not accessed on a normal boot. BUG=b:119435206 TEST=tested on Arcada board to ensure expected regions are present Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10mb/google/hatch: enable CPU cluster deviceAamir Bohra
Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30785 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10aopen/dxplplusu: Move timestamps to common codeKyösti Mälkki
First initialisation is already in cpu/intel/car/romstage.c. Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10mb: Move timestamp_add_now to northbridge/amd/amdfam10Elyes HAOUAS
Also remove some commented code. Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-12 11:49:34 +0000