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2019-02-05mb/intel/coffeelake_rvp: Select CHROMEOS for CFL-U and WHL-U RVPSubrata Banik
This patch ensures to select chromeos kconfig only for required CFL-U and WHL-U RVPs supported by Intel client team. TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected for CFL-U and WHL-U boards. Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31214 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05mb/google/sarien: Set system type for the board variantsDuncan Laurie
Select the appropriate system type for the different variants of the Sarien board. This will allow the Arcada variant to use the tablet mode feature of the Intel Virtual Button driver. Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add keyboard backlight supportIvy Jian
This change adds keyboard backlight feature for Hatch platform. BUG=b:122799544 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I29273122f061e0e442f6629351ef3670535c0507 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31175 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05mb/google/poppy/variants/atlas: config GPP_D1 as no-connectCaveh Jalali
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really doesn't go anywhere today or on previous revs of the board. BUG=b:110614620 BRANCH=none TEST=atlas still boots Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"Caveh Jalali
This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8. We're seeing trackpad problems on some units with the I2C bus running at 1MHz but not at 400KHz. So, revert back to 400KHz until we understand how to make 1MHz operation more robust. BUG=b:123650686 Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/kukui: Add default HWID for Chrome OSHung-Te Lin
The default value for Chrome OS HWID should be different. Calculated as HWID v1. BUG=b:123336677 BRANCH=kukui TEST=build and boots properly. Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05mb/emulation/qemu-i440fx: use e820 in romstageThomas Heijligen
Use memory map from fw_cfg e820 map to find cbmem_top in romstage to avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as fallback. Change-Id: I6465085020125fc790257f09eb157030c6ceabcb Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05mb/emulation/qemu-i440fx: make fw_cfg_present usable in PRERAMThomas Heijligen
Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05mb/emulation/qemu-i440fx: add e820 interfaceThomas Heijligen
Qemu provides e820 table at fw_cfg interface. Add functions to access it. Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05mb/emulation/qemu-i440fx: remove mm file listingThomas Heijligen
Remove memory mapped copy of the file list to use it also in romstage. fw_cfg_find_file searches directly for the file on data port. Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh
These boards need a working VTD therefore enable this feature. Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-02-05mb/google/octopus: Add USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add USB port capability ACPI support for USB2 port10Aamir Bohra
This implementation adds support to create ACPI package for USB port capability (_UPC) and physical location of device (_PLD) for USB2 port 10. BUG:b:123375275 TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10 in SSDT and BT is functional in discrete and integrated mode. Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31197 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT KconfigSubrata Banik
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-02mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGIONPatrick Rudolph
It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE. Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-02mb/intel/coffeelake_rvp: Enable GBE region for RVP8 and RVP11Subrata Banik
This patch ensures to enable IFD GBE region only for required CFL RVP8 and 11 supported by Intel IOTG team. TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected for CFL-U and WHL-U boards Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-01mb/google/hatch: Enable S0ixShelley Chen
BUG=b:123540469 BRANCH=None TEST=None Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31157 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/sarien: Turn on ASPM L1.2 for Card ReaderLijian Zhao
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/octopus: Add Bluetooth USB ACPI configurationKarthikeyan Ramasubramanian
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI configuration in devicetree. This change enables exporting the bluetooth reset GPIO to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-31mb/emulation/qemu-i440fx: prepare fw_cfg for romstage usageThomas Heijligen
Add separate functions for selecting the port and reading the port. Romstage can now read incremental from the data port. Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-31mb/emulation/qemu-i440fx: change file handlingThomas Heijligen
Reduce the number of fw_find_file calls by returning the file structure at fw_cfg_check_file. The file structure can then be used to allocate memory and access the file content directly without recurrence searching. Remove now unnecessary function fw_cfg_load_file. Fixed breaking function calls and add include guard at fw_cfg_if.h. Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/30845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-31google/kukui: Set GPIO_RESET to output modeTristan Shieh
In payloads, we didn't set GPIO modes. We have to set up GPIO mode in coreboot for payloads. BUG=b:80501386 BRANCH=none TEST=HW reboot works in depthcharge Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31148 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31lib/hardwaremain: Fix more ACPI/IOAPIC typosSubrata Banik
CB:31139 fixs few ACPI type error. Here is few more typo mistake. Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31152 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mainboard/intel/cannonlake_rvp: Enable SaGv configRonak Kanabar
This patch enables SaGv on Intel CNL-Y and CNL-U RVP board Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31132 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mainboard/{google,intel}: Remove SaGv hard codingRonak Kanabar
Remove hard coding for SaGv config in devicetree.cb and apply macro for SaGv config for CNL variants boards Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-30mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet specCasper Chang
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-30siemens/mc_apl2: Change SERIRQ modeMario Scheithauer
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47. Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31138 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer
Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-30siemens/mc_apl2: Activate TPM supportMario Scheithauer
The TPM chip is connected to the SPI interface of APL. The proper chip select pin needs to be used in order to access the TPM in the memory mapped space. This needed chip select is internally (inside APL) routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to make the TPM work on SPI bus. TEST=Build coreboot for mc_apl2 board and check the TPM console output. In addition the TPM was correctly verified by our Linux driver. Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-30mb/google/octopus/casta: Correct unused GPIO pad configurationSeunghwan Kim
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad. This patch corrects the configuration. BUG=NONE BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-30mb/google/hatch: Enable AP Wake from ECShelley Chen
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake the AP from suspend. Also create a task to initialize the hostevent wake mask properly. BUG=b:123325238,b:123325720 BRANCH=None TEST=from AP console: powerd_dbus_suspend from EC console: hostevent (make sure wake mask set) from EC console: gpioset PCH_WAKE_L 0 Make sure device wakes up Also, checked to make sure keyboard press wakes up device from S3. Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-29mb/google/octopus/var/phaser: Hook up Raydium touchscreenHao He
List Raydium touchscreen in the devicetree so that the correct ACPI device are created. BUG=b:121105424 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT, make sure the Raydium touchscreen can work. Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31116 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29google/kukui: Move some initialization from bootblock to verstageYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29google/kukui: Implement HW reset functionTristan Shieh
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29mediatek: Separate WDT reset function from WDT driverTristan Shieh
Separate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset function on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to pass the build for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31121 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29mb/lenovo/z61t/Kconfig: Select I945_LVDSPeter Lemenkov
This board has almost the same schematics as [xt]60 so this should work. See also commit 7971582e with Change-Id Iff6dac5a5f61af49456bc6312e7a376def02ab00. Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-29mb/intel/icelake_rvp/../icl_y: Enable SaGvSubrata Banik
This patch enables SaGv on Intel ICL-Y RVP board. TEST=Able to build and boot to Chrome OS. Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-28mb/asus/h61m-cs: Add ASUS H61M-CSdevmaster64
Working: - USB (Partially. Check "Not working") - PCIe - PCIe graphics - All SATA ports - Native memory init - On-board audio (back and front) - S3 (Sleep and wake) Not working: - Fan control - USB (If the keyboard has a USB Hub or if the keyboard is connected through 2 or more hubs then it doesn't initialize in time. A simple reboot allows the keyboard to be used in SeaBIOS and the bootloader) Untested: - PS/2 - On board graphics Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2 Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com> Reviewed-on: https://review.coreboot.org/c/30767 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28mb/google/octopus: Fix termination for unused dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequencySeunghwan Kim
ELAN touchpad supports up to 400KHz, so we need to limit its CLK frequency to 400HKz. BUG=b:123376618 BRANCH=octopus TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mb/lenovo/thinkcentre_a58: Extend mb nameArthur Heymans
While branded as thinkcentre a58 this board can also be found as "L-IG41M". Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-28mb/google/sarien: Using HID over I2C to enable Melf TouchScreenChris Zhou
Current Melfas touchscreen driver cannot unregister ifself when connecting without Melfas touchscreen or connecting with other devices. And Melfas touchscreen FW can use I2C and HID over I2C driver, so switch to using HID over I2C driver. BUG=b:122710830 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 Reviewed-on: https://review.coreboot.org/c/31062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-26mb/qemu-riscv: update to match current qemu versionPhilipp Hug
Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25mb/lenovo/x131e: remove PMH7James Ye
This board does not have PMH7. Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31065 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/denverton_ns: Enable ACPI using intelblockJulien Viard de Galbert
- Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25mb/google/octopus: Override emmc DLL values for AmptonKane Chen
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25mb/google/sarien: Force power on after cr50 updateDuncan Laurie
By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25mb/google/sarien: Increse BIOS region size to 28MBLijian Zhao
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25mb/google/kahlee/variants/aleena: Add support Synaptics touch padLucas Chen
Add support Synaptics touch pad for Aleena/Kasumi. BUG=b:122549449 BRANCH=master TEST= Check if synaptics touch pad working in ChromeOS. Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31064 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that ↵Jan Tatje
need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 05:37:31 +0000